1. 1 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy Data transmission and selection for the L0 calorimeter trigger of LHCb G. Avoni (INFN – Bologna – Italy)

2. 2 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy Introduction The L0 trigger system of LHCb is used to reduce the bunch crossing rate of LHC (40.08 MHz) to the 1 MHz rate sustainable for the High Level Trigger. The calorimeter system of LHCb is used to select the highest energetic clusters in the ECAL (electromagnetic calorimeters) or HCAL (hadronic calorimeters) for the L0 calorimeter trigger. The 32 channels front end board selects a cluster as a 2x2 local maximum energy deposit. Signal from the auxiliary detectors SPD and Pre-Shower are used in the Validation phase to assess the cluster type (Particle Identification). The cluster energy is measured on 2x2 cells at the front-end board, from 8x8 cm 2 (inner ECAL) to 52x52 cm 2 (outer HCAL). ECAL is segmented in 5952 cells (each cell is a possible cluster). Validation (to determine the cluster type) is done by the PS/SPD (same geometry) to get the electron and photon candidates. Combination of the detector signal to select π 0 candidates are also foreseen. HCAL is segmented in 1484 cells (each cell is a possible cluster). Addition of the energy possibly lost in ECAL if available.

3. 3 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy L0 Calorimeter Trigger L1 Buffer FE boards 8x4 input channels Validation Cards 10m cables LVDS connections Optical links (100m fibers) Selection Boards Optical links (5m fibres)

4. 4 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy TOP SIDE VIEW GOL VCSEL BOTTOM SIDE VIEW Single-Channel TX Clock 40,08MHz Controls 32 data bits Power GOL (Gigabit Optical Link, CERN) VCSEL (Vertical Cavity Surface Emitting Laser) ULM850-05-TN-USMB0P 850nm,1mW@6mA made by ULM Photonics Connectors 40 mm “READY” Status LED SAMTEC QTS/QSS series Hi-Speed 0.635mm pitch connectors GOL I 2 C address setting “FAULT” Status LED SMA connectors Power LED Assembled and tested: 16 (PreShower & SPD) + 24 (SB) + 10 (spares) = 50 boards VCSEL bias current setting

5. 5 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy 40MHz Control 12x32 bits data GOL x 4 Parallel Fiber trasducer AGILENT HFBR-772BH Clock distributor NB100LVEP221 Power GOL x 4 Control 12x32 bits data Power Control & Power 2x 250 pin SAMTEC connectors 116 mm. TOP SIDE VIEWBOTTOM SIDE VIEW Multi-Channel TX Assembled and tested: 28 (VC) + 44 (CROC) + 28 (spares) = 100 boards MAIN FEATURES: - 8 independent electro- optical transducers accept 8x32-bit at 40.08MHz; - 1 multimode 850nm 50/125u optical ribbon fiber with MPO connector; - 2 independent JTAG chains; - I2C bus for individual GOL addressing; GOL I2C address setting AGILENT HFBR-772BH MPO receptacle with guiding pins CROC= Calorimeter Readout Optical Cards VC=Validation Cards

6. 6 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy BER Measurement Transmitting side DG2040 Tektronix 40MHz Textronix TLA720 Logic analyzer Pattern Generator 32bit@40MHz. Xilinx FPGA REF (Delayed TXDATA) 80 mt. Optical Fiber Agilent HFBR-772BH optical receiver and pattern comparator tx_en Testing time: from 5hrs up to 1 day. In a range of attenuation values between 0 and 8dB, the results show that the BER is better than 10 -13 as expected. In the final conditions, the measured attenuation of the entire optical path is less than 1dB. Clock generator 40 MHz 80 MHz FPGA clock Result 32bits DATA 32bits TXDATA 32bits TXDATA=REF ? If YES, Result=1 If NO, Result=0 Receiving side For prototype qualification TX under test Amphenol AFO 46946 attenuator

7. 7 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy BER Measurement II TX synchronization - This logic analyzer screenshot shows how the receiver got synchronized by IDLE patterns. Generated pattern (DATA)Received pattern (TXDATA)Comparator Result

8. 8 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy Selection Board (SB) Main Features 8 SB hosted in the Selection Crate are needed to perform the entire data selection (4 additional boards as spare). Trigger information to the L0DU: selection of the highest energy candidate for each particle type; complete cluster address translation, converting the 8-bit address in the 14-bit address by means of a dedicated Look-Up-Table (LUT); computation of the total HCAL energy release and the SPD multiplicity that are used as auxiliary trigger information (for example, an empty or a too complex event to be rejected); Trigger information to the HLT: In case of L0-accepted events, all the input and output data of the SBs are moved forward to the TELL1 boards. The hardware of the SB boards is identical, but individually programmed depending on the required selection task to be performed.

9. 9 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy SB Overview SCHROFF 4TE Front panel with handles TTCrq module with plastic ST optical input for TFC External CLOCK CLOCK distributor 32-bits local bus test header Control FPGA Process FPGA XILINX XC2VP40 CCPC CMOS battery Power source Report board I/O port Configuration jumpers Glue Card CCPC Process LUT AT28LV010 3 optical transmitters 5 Input FPGAs XILINX XC2VP20 3 Metal bars for thermal and mechanical stability FPGA’s power regulators 6 x 5 x TLK2501 deserializers 3 Agilent HFBR782BH MPO 12_channels optical inputs Input FPGA optional expansion ports

10. 10 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy SB Technical Features PHYSICAL: - VME 9U/4TE standard, 2.6 mm PCB thickness, 16 PCB layers; - Controlled impedance paths designed for critical signals (i.e. clock, serial data); - Similar length of the traces between different deserializers; FUNCTIONAL: 30 optical inputs (28+2 spares) suited for MPO-F connectors and ribbon of 12 fibers; 3 optical outputs, suited for single-fiber SMA connector boards, carrying event information such as total energy, total sum, L0 trigger; On-board programming and debugging hardware (4 x I2C buses, 3 x JTAG chains, 1 x 32 bits parallel multiplexed local bus, optional expansion ports); Automatic logic block for input data alignment; ECS-addressable Look-Up-Table (LUT) provided for event address translation from 8bits to 14bits (the process FPGA automatically loads its on-board LUT at start-up); ECS-addressable input and output FIFOs, provided to check the correct data flow during normal operation of the entire selection process; Capability of inter-board communication, through a dedicated interface and a point-to- point connector (feature used in the HCAL, which requires 3 SBs to handle 80 optical channels); Temperature sensors for monitoring of several areas of the board;

11. 11 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy SB Input Logic Input FPGA XILINX XC2VP20: project implementation overview er dv 16 er dv In Pad DeMux 16 to 32 DATA ALIGNMENT FIFO Diagnostic FIFO 32x256 Manual delay Data 16 Data Valid 32 Out Pad ECS BCrst from TTCrq Channel Enable from ECS Write logic Receiving Clock System Clock Read logic ECS To Process FPGA From TLK2501 deserializer Receiving Clock domain System Clock domain BER test ECS Ch1 Ch2 Ch3 Ch5 Ch4 Ch6 Link error dverData type 00Idle patterns 10Normal data 11Link error 01Carrier extend ECS enable Delay ECS-programmable pattern generator and comparator with errors counter This FIFO can store up to 256 events to check the correct dataflow ECS

12. 12 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy SB Process Logic In U2 In pad Mask & Ghost 3x FIFOs Acquire 32x256 Connectivity test 3 x ECS Registers Out Pad ECS ACQUIRE 8 to 14 bits address LUT Max & Sum ECS Max & Sum Mux Derandomizer In U3 In U4 In U5 ECS Out Pad Mux To Tx LODU2 Out Pad Mux To Tx TELL1 ECS Report register To Tx LODU1 To report board connector Max ECS L0_Accept Diagnostic pattern generator ECS Process FPGA XILINX XC2VP40: project implementation overview In U1 (Ghost function only for Hadron) Address translation from local to global ECS Sum

13. 13 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy SB Control Panels Board general state: - READY - TEST - CONFIG - ERROR SBs list Crate status detail: - READY - TEST - CONFIG - ERROR Crate message log Board detailed status Board message log Board name Enter the output test procedures

14. 14 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy SB Debugging The assembling has been done by an external company. During the debugging, a few “common” issues needed to be fixed. Nevertheless, the overall quality is outstanding. Ceramic capacitor badly soldered Tantalum capacitor reverse mounted HFBR-782BH 10x10 array socket CORRECTLY oriented BADLY oriented

15. 15 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy SB Installation Installation of the first SB at Point 8, CERN, April 2007 SB-dedicated point-to-point connector The SB layout in the Selection Crate (note the 3 joined SB for Hadron)

16. 16 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy SB Test Results First acquisition results, CERN, May 2007 An HCAL response to LED pulses simulating a high energy deposit. The event has been triggered and reconstructed.

17. 17 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy Conclusions Optical TX - We built up 150 optical transmitter modules for the LHCb calorimeter system, needed both for the L0 trigger and data acquisition. - We successfully tested the entire set of single- and multi-channel optical TX modules. - They have already been tested by plugging them to their carrier main boards. - The optical TX modules behave as expected. Selection Boards - 12 boards have been produced and globally tested in our lab in Bologna. - A first board has been successfully installed last April at CERN.

18. 18 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy Input Data Alignment Channel 1 DataValid For each channel, an asynchronous FIFO has been implemented in the input FPGA. Each input channel is written to the left port of its FIFO independently from the others. The write logic is triggered by the “DataValid” signal. Channels are read out all together from the right port of all FIFOs, after a programmable number of cycles. The read logic is triggered by the “BCRST” signal, coming from TTC system. Channel 2 DataValid Global BCRST signal System clock ALIGNED DATA There is a well-known issue about the variable latency of the ser/des devices. Due to silicon process variations and implementation variables such as supply voltage and temperature, the timing of the data flow is affected (for example, in the same hardware setup, two data buses start together before entering the TX, but arrive delayed at their RX deserializer output bus). The transmit latency is fixed once the link is established.

19. 19 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy BER vs. Attenuation Optical data will go through 100m long cables and two optical patch panels (total attenuation less than 1dB). A range of attenuation values have been tried out to measure the real power margin and keep the transmission error-free. Amphenol AFO 46946 optical attenuator Attenuation (dB)Time (hrs.)Errors 024/ 3 / 6120/ 924/ 1224/ 1424Some

20. 20 TWEPP 2007, Prague, Czech RepublicG. Avoni – INFN, Bologna, Italy The 8bit/10bit Encoding All true serial interfaces require a method of encoding to insure minimum transition density so that the receiving PLL has a minimal number of transitions to stay locked on. The encoding scheme maintains the signal dc balance by keeping the number of ones and zeros the same. This provides good transition density for clock recovery and improves error checking. The TLK2501 uses the 8-bit/10-bit encoding algorithm that is used by the fibre channel and the gigabit ethernet (this is transparent to the user, as the TLK2501 internally encodes and decodes the data such that the user reads and writes actual 16-bit data). The real serial bitrate in the fiber is 20bit x 2 x 40 MHz.= 1,6GBps. Here are few lines extracted from the 8B/10B coding table: Code Group Name Octet Hex Value Octet BitsRunning disparity –Running Disparity + D0.0 00000000001001110100 (5 ones and 5 zeroes) 0110001011 (5 ones and 5 zeroes) D18.0 12000100100100111011 (6 ones and 4 zeroes) 0100110100 (4 ones and 6 zeroes) D27.3 7B011110111101100011 (6 ones and 4 zeroes) 0010011100 (4 ones and 6 zeroes) D31.7 FF111111111010110001 (5 ones and 5 zeroes) 0101001110 (5 ones and 5 zeroes) For further information about synchronization using GOL with TLK2501, refer to Technical Note LHCb 2004-012.