1. Lab 9 Multiprocessor, Buses, SPI, I2C

2. Multiprocessors Why multiprocessors? The structure of multiprocessors. Elements of multiprocessors: – Processing elements. – Memory. – Interconnect.

3. Why multiprocessing? True parallelism: – Task level. – Data level. May be necessary to meet real-time requirements.

4. Multiprocessing and real time Faster rate processes are isolated on processors. Slower rate processes are shared on a processor (or processor pool). CPUmem CPUmem print engine File read, Rendering, Etc.

5. Heterogeneous multiprocessors Will often have a heterogeneous structure. – Different types of Process Elements. – Specialized memory structure. – Specialized interconnect.

6. Multiprocessor system-on-chip Multiple processors. – CPUs, DSPs, etc. – Hardwired blocks. Custom memory system. Lots of software.

7. System-on-chip applications Sophisticated markets: – High volume. – Demanding performance, power requirements. – Strict price restrictions. Often standards-driven. Examples: – Communications. – Multimedia. – Networking.

8. Terminology PE: processing element. Interconnection network: may require more than one clock cycle to transfer data. Message: address+data packet.

9. Generic multiprocessor Shared memory: Message passing: PE mem PE mem PE mem … … Interconnect network PE mem PE mem PE mem … Interconnect network

10. Shared memory vs. message passing Shared memory and message passing are functionally equivalent. Different programming models: – Shared memory more like uniprocessor. – Message passing good for streaming. May have different implementation costs: – Interconnection network.

11. Shared memory implementation Memory blocks are in address space. Memory interface sends messages through network to addressed memory block.

12. Message passing implementation Program provides processor address, data/parameters. – Usually through API. Packet(s) interface appears as I/O device. – Packet routed through network to interface. Recipient must decode parameters to determine how to handle the message.

13. Processing element selection What tasks run on what PEs? – Some tasks may be duplicated – Some processors may run different tasks. How does the load change? – Static vs. dynamic task allocation.

14. Parallel memory systems True concurrency--- several memory blocks can operate simultaneously. PE mem PE mem PE mem … … Interconnect network

15. Cache consistency Problem: caches hide memory updates. Solution: have caches snoop changes. PE mem PE cache network mem

16. Cache consistency and tasks Traditional scientific computing maps a single task onto multiple PEs. Embedded computing maps different tasks onto multiple PEs. – May be producer/consumer. – Not all of the memory may need to be consistent.

17. Bus network Advantages: – Well-understood. – Easy to program. – Many standards. Disadvantages: – Contention. – Significant capacitive load.

18. USCI The universal serial communication interface (USCI) supports multiple serial communication modes with one hardware module: – UART mode – I2C mode – SPI mode

19. UART mode Universal Asynchronous Receiver Transmitter (UART) provides serial communication. In UART mode, the USCI transmits and receives characters at a bit rate asynchronous to another device. Timing for each character is based on the selected baud rate of the USCI. The transmit and receive functions use the same baud rate frequency.

20. Serial communication Only P2P communication Characters are transmitted separately: time bit 0bit 1bit n-1 no char start stop... One character

21. Serial communication parameters Baud (bit) rate (=1/period of one bit) Number of bits per character (5-8) parity/no parity (whether parity to be included) Even/odd parity (if parity included, its value) Length of stop bit (1, 2 bits).

22. UART: character format

23. I2C I²C (Inter-Integrated Circuit) is a multi-master serial computer bus invented by Philips that is used to attach low-speed peripherals to a CPU, embedded system, or cell phone. I²C uses only two bidirectional open-drain lines, Serial Data (SDA) and Serial Clock (SCL), pulled up with resistors. Typical voltages used are +5 V or +3.3 V although systems with other, higher or lower, voltages are permitted.

24. I2C The I²C reference design has a 7-bit address space with 16 reserved addresses, so a maximum of 112 nodes can communicate on the same bus. The most common I²C bus modes are the 100 kbit/s standard mode and the 10 kbit/s low-speed mode. Recent revisions of I²C can host more nodes and run faster (400 kbit/s Fast mode, 1 Mbit/s Fast mode plus or Fm+, and 3.4 Mbit/s)

26. I2C The bus has two roles for nodes: master and slave: Master node — node that issues the clock and addresses slaves Slave node — node that receives the clock line and address. The bus is a multi-master bus which means any number of master nodes can be present. Additionally, master and slave roles may be changed between messages (after a STOP is sent). There are four potential modes of operation for a given bus device, although most devices only use a single role and its two modes: master transmit — master node is sending data to a slave master receive — master node is receiving data from a slave slave transmit — slave node is sending data to a master slave receive — slave node is receiving data from the master

27. I2C The master is initially in master transmit mode by sending a start bit followed by the 7-bit address of the slave it wishes to communicate with, which is finally followed by a single bit representing whether it wishes to write(0) to or read(1) from the slave. If the slave exists on the bus then it will respond with an ACK bit (active low for acknowledged) for that address. The master then continues in either transmit or receive mode (according to the read/write bit it sent), and the slave continues in its complementary mode (receive or transmit, respectively). If the master wishes to write to the slave then it repeatedly sends a byte with the slave sending an ACK bit. (In this situation, the master is in master transmit mode and the slave is in slave receive mode.) If the master wishes to read from the slave then it repeatedly receives a byte from the slave, the master sending an ACK bit after every byte but the last one. (In this situation, the master is in master receive mode and the slave is in slave transmit mode.) The master then ends transmission with a stop bit, or it may send another START bit if it wishes to retain control of the bus for another transfer (a "combined message").

28. I2C I²C defines three basic types of message, each of which begins with a START and ends with a STOP: 1. Single message where a master writes data to a slave; 2. Single message where a master reads data from a slave; 3. "Combined" messages, where a master issues at least two reads and/or writes to one or more slaves.

29. I2C arbitration Every master monitors the bus for start and stop bits, and does not start a message while another master is keeping the bus busy. However, two masters may start transmission at about the same time; in this case, arbitration occurs. Slave transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. In contrast to protocols (such as Ethernet) that use random back-off delays before issuing a retry, I²C has a deterministic arbitration policy. Each transmitter checks the level of the data line (SDA) and compares them with the levels it expects; if they don't match, that transmitter has lost arbitration, and drops out of this protocol interaction.

30. Serial Peripheral Interface (SPI) Bus A synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial buses. All devices are at the same voltage level The SPI bus can operate with a single master device and with one or more slave devices.

31. SPI logic signals The SPI bus specifies four logic signals. SCLK — Serial Clock (output from master) MOSI/SIMO — Master Output, Slave Input (output from master) MISO/SOMI — Master Input, Slave Output (output from slave) SS — Slave Select (active low; output from master)

33. PCI The Peripheral Component Interconnect, or PCI Standard specifies a computer bus for attaching peripheral devices to a CPU. These devices can take any one of the following forms: An integrated circuit fitted onto the CPU itself, called a planar device in the PCI specification. An expansion card that fits into a socket.

34. PCI provides two separate 32-bit or 64-bit address spaces corresponding to the memory and I/O port address spaces of the CPU. Addresses in these address spaces are assigned by software. A third address space, called the PCI Configuration Space, which uses a fixed addressing scheme, allows software to determine the amount of memory and I/O address space needed by each device. Each device can request up to six areas of memory space or I/O port space via its configuration space registers. In a typical system, the firmware (or operating system) queries all PCI buses at startup time (via PCI Configuration Space) to find out what devices are present and what system resources (memory space, I/O space, interrupt lines, etc.) each needs. It then allocates the resources and tells each device what its allocation is. Each device is a master whenever uses its timeslot.