1. Verification for Ethernet second/first layer with 10 Gigabit Attachment Interface (XAUI) Matan Kacen Intel, ICG, LAD HW AV June 2005 Dr. Nissim Tsouri Department of Communication Systems Engineering Mr. Aviah Hevrony AV core team leader Lan Access Division Intel Communication Group

2. Project goal To create a generic Test Bench (Verification environment) for Ethernet over 10 Gigabit Attachment Unit Interface (XAUI) as defined in the IEEE802.3.ae standard.

3. Pre silicon validation Validation of the RTL design before the production of silicon. Validation of the RTL design before the production of silicon. White box validation. White box validation. Two main steams : Two main steams : –Random validation –Direct validation –As always the optimize way is somewhere in between –The project need to support both.

4. Test bench environment The TB “warp” the design and implement all the interface that is around it. The TB “warp” the design and implement all the interface that is around it. Normally we drive a transaction from one interface, collect it from the other and compare according to the expected design behave. Normally we drive a transaction from one interface, collect it from the other and compare according to the expected design behave. Device Under Testing DUT (RTL design) Interface AInterface B Clocks Interface C

5. 10 Gigabit Ethernet

6. XAUI Protocol XAUI interface is a 16 pins, 8 lanes (4 TX, 4 RX) differential interface. XAUI interface is a 16 pins, 8 lanes (4 TX, 4 RX) differential interface. The clock is embedded within the differential signals and runs at 3.125 GBaud. (320 ps Unit interval nominal) The clock is embedded within the differential signals and runs at 3.125 GBaud. (320 ps Unit interval nominal) Symmetric interface architecture. Symmetric interface architecture. In the TX side, encoding of 4 XGMII lanes (Data & control) into 4 XAUI lanes. Each one is self clocked, serial, 8B/10B encoding data stream. The encoding is define in 802.3.ae standard clause 48. Each lane transmit the data serially. In the TX side, encoding of 4 XGMII lanes (Data & control) into 4 XAUI lanes. Each one is self clocked, serial, 8B/10B encoding data stream. The encoding is define in 802.3.ae standard clause 48. Each lane transmit the data serially. In the RX side, recovers the clock and data from each XAUI lane and deskew the four XAUI lanes into single clock XGMII. In the RX side, recovers the clock and data from each XAUI lane and deskew the four XAUI lanes into single clock XGMII.

7. XAUI Protocol – Block diagram RX unaligned 4xlane n SYNCHRONIZE DESKEW RECEIVE XGMII: RXD RXC RX_CLK XGMII: TXD TXC TX_CLK TRANSMIT TX 4xlane n

8. XAUI Protocol – data flow XAUI

9. The Test Bench Architecture Divide the TB into 2 layers using inheritance relationship between them : Divide the TB into 2 layers using inheritance relationship between them : –Ethernet layer - simulate the link partner and the LAN : generate Ethernet frames, IPG (Inner packet gap) handling, collision (In lower speeds) … –Protocol layer – simulate the specific protocol using between the Physical layer and the Data link layer : Interface behave, link errors, encoding & decoding the data, idle stream generation …

10. Tools The TB is written in the verification language e (Specman). The TB is written in the verification language e (Specman). The advantages of Specman: The advantages of Specman: –It can connect to any RTL design written in VHDL or Verilog. –It has the ability to force signals into the design. –Zero time forcing signals (Instillation) –Sample signals from the design. –Multi thread run time process. –Random generator. –Create events upon changes / events that happen in the design signals. –Collect coverage on predefined events and behavior. –Check DUT behavior.

11. The Test Bench Architecture eRM compiled

12. Relationship between the Ethernet Layer and the XAUI layer We used a “pipe line” design for the micro architecture. We used a “pipe line” design for the micro architecture. In the inject size the data (frame) pass several function cross between the layers until it is injecting on the interface signals In the inject size the data (frame) pass several function cross between the layers until it is injecting on the interface signals

13. BFM (BUS Functional Model ) example Ethernet Flow פונקציות שממומשות ברמת ה Ethernet פונקציות ריקות ברמת ה Ethernet שעיקר מימושם ברמת הפרוטוקול פונקציות שמאפשרות למשתמש גישה למידע הזורם ב Pipeline. CB Frames Add frame events Pack list of bits List of bits  list of symbol Add line events Send data CB Wait IPG

14. XAUI BFM architecture Frames Pack – List of bits Symbol matrix – Column & lanes Add line events on symbols Main loop @CLK (312.5 Mhz) Symbols XAUI arb @CLK (312.5) IDLE Generator Lane injector Lane encode & inject @CLK 3.125 GHz CB Lane encode & inject @CLK 3.125 GHz Lane encode & inject @CLK 3.125 GHz Lane encode & inject @CLK 3.125 GHz CB

15. User interface Easy interface to connect the component the global validation environment (The minimum is to connect the signal map). Easy interface to connect the component the global validation environment (The minimum is to connect the signal map). User can monitor & manipulate data using Call Back function along the data flow. User can monitor & manipulate data using Call Back function along the data flow. The user can use the Config strutre to change the TB behave. The user can use the Config strutre to change the TB behave. The TB give log file (trackers) on the data for debug use. (Both symbol and packets) The TB give log file (trackers) on the data for debug use. (Both symbol and packets)

16. How does it looks (Specman GUI)

17. Q&A