1. Discrete logic processor
Technical presentation
John Duffy

2. Background
I started this project while I was a Junior in High School. One of the mentors for a robotics team I was on was talking about a college course of his where they had to build a computer (using an Intel 8080). I realized that I had no idea how a processor actually executes code.
I spent a few weeks reading books online during lunch and between classes.
When I finally had a basic idea of how all the parts worked together, it seemed so simple that I could do it myself, so I started thinking about a full system layout of my own.
Once I had a simulation working in logisim, I figured that there were few enough parts that I could build actual hardware for it.
I discussed the idea with another mentor on my robotics team, who told me about wire wrap, and gave me a pair of wire wrap boards to use, and some advice on working with digital logic chips.

3. Operation A addrs RAM A data C addrs (128x8) C data A ROM Opcode
Registers
A data
A addrs C
data
B addrs
B data
(256x32) B
address
C addrs
C data
C data
ALU
C data
Program Counter
B addrs
B data
C addrs
C data
Counter

4. Simulation
Once designed on paper, I moved to a simulator, logisim, to test the design.
At first, I had to write the files by hand in binary, then convert them to hexidecimal.
To make writing programs easier, I wrote a simple assembler in java, to abstract variables and jumping to lines.
Overall, I went through 23 iterations before arriving at the design that I actually built.

5. Hardware
Once I had something that worked well in simulation, I started building the hardware.
Instead of an actual ROM, I used an arduino Mega, to make it easier to program and debug. It doesn't offload any of the processing, it just acts as the system clock, a 256x32 bit ROM and a pair of buffers. It could be easily replaced with an oscillator and one or more ROM chips.
The logic is made with 74' series CMOS logic gates, using a wire wrap board for connections. The RAM is a 25ns 8 bit SRAM.

6. Hardware
The logic was built up in sections, starting with the program counter, then RAM, ALU, bus control, data register, and output registers.
Each part was bread boarded first and tested for speed and consistency. Most passed perfectly, but the RAM logic was inconsistent.
Referring to the waveform showed that the timing around the RAM was very close, and therefore it often often the data on the A data bus instead of C. This was fixed with two capacitors and a resistor, which introduced a small delay between the clock edge and latch. While not a perfect solution, testing found that it worked very consistently, so it was acceptable.