1. AFOSR/AFRL Center of Excellence: The Science of Electronics in Extreme Electromagnetic Environments
MOSFET Defect Enhanced Vulnerability to Terminal Voltage Stress: A DFT and FEM Based Analysis Chris Darmody, Dev Ettisserry and Neil Goldsman Department of Electrical and Computer Engineering University of Maryland College Park

2. Overview Introduction: nano-MOSFETs and Vulnerability
Dielectric Breakdown and Tunneling Analysis with FEM
Role of Oxide Defects in EMI Vulnerability
Atomic Level Modeling of Defects & High Gate Voltage:
Density Functional Theory (DFT) plus related modeling tools.
Model Agreement of MOS Oxide Charging with Exp.
Summary and Future Work 1

3. Standard MOSFET (3D) An Integrated Circuit can contain a billion MOSFETs
Width ~ 50nm
SiO2 Thickness
~ 2 nm
Length
~ 20nm 2

4. Fermi Level: Relative Position vs. Bias
MOS System 3

5. Printed Circuit Board (PCB) Contains chips and metal lines
EMI can induce voltage variations on PCB traces that make their way to device terminals causing unexpected potential differentials on micro and nano device contacts. 4

6. FinFETs and Materials: New FinFET vs. Old Standard MOSFET
P-Substrate
Wafer Thick
N-Source
N-Drain
Gate Oxide VS VG VD
Channel
New FinFET Vertical Design; Stands up like a fin.
Old Bulk Design 5

7. FinFET Design and Advantages
Intel Corp.
Design:
High-k gate dielectric for thin equivalent oxide thicknesses (sub 2nm)
Thin SiO2 layer at interface between high-k dielectric and substrate (1nm)
Rounded corners reduce premature inversion
Advantages:
Density scaling beyond planar devices (sub 20nm)
Large effective channel width
Lower threshold and source-drain leakage (fully depleted channel)
[1]
HfO2
SiO2
p-Si
[1] Wu et al, High Performance 22/20nm FinFET CMOS Devices with Advanced High-K/Metal Gate Scheme (2010) 6

8. Dielectric Defects and Breakdown in FinFETsVG
Gate Metal
Oxide
Si Fin
Non-uniformity
Direct
Tunneling
Leakage
Defects/Traps
Trap-assisted
Tunneling Leakage IG
tox
Oxide imperfections from processing
Variations of oxide thickness
Carrier tunneling breaks weak oxide bonds which form conducting paths
Breakdown through defect paths
Saraswat, Thin Dielectrics for MOS Gate 7

9. FinFET Vulnerabilities
High-k dielectrics more trap-rich, degrading device performance
Gate voltage stresses cause trap generation
Traps increase gate leakage
Soft breakdown: weak conduction through single-trap path
Progressive breakdown: trap assisted tunneling
Hard breakdown: critical trap concentration and/or critical electric field
Less robust to oxide degradation than lateral MOSFETs
Soft Breakdown
Progressive Breakdown
Hard Break-down
IG [A]
Breakdown curve of SiO2/HfO2 gate dielectric layer
Fenfen et. al, TDDB characteristic and breakdown mechanism of ultra-thin SiO2/HfO2 bilayer gate dielectrics (2014) 8

10. Analyzing Dielectric Reliability from EMI in FinFETs
Solve Poisson equation in fin using the Finite Element Method (FEM)
Obtain values for:
Potential (ϕ)
Electric field ( 𝐸 )
Electron concentration (n)
Hole concentration (p)
everywhere inside fin for
applied gate biases VG
EMI IG 9

11. Solving Poisson Equation with FEM
𝛻 ∙ 𝜺 𝒓 𝛻𝝓 = 𝑞 𝜀 0 ( 𝒏 𝟎 𝑒𝑥𝑝 𝑞𝝓 𝑘𝑇 − 𝒏 𝟎 𝑒𝑥𝑝 −𝑞𝝓 𝑘𝑇 + 𝑵 𝑨 − − 𝑵 𝑫 + ) n p
dopant ions
Replace PDE with linear system of coupled equations on discrete mesh
Solve matrix equation
Finer mesh near important regions
Interpolate with piecewise-continuous polynomials
Advantages of FEM over Finite Difference:
Able to handle complicated geometries + boundaries easily
Error estimates and convergence rates wrt. element size
Automatically enforces jump conditions at internal interfaces
Formulation ensures discrete solution is the best approximation to real solution wrt. energy norm 10

12. Voltage in Fin (SiO2)
Volts
VG=1V
VB=0V 11

13. Electric Field at Interface (SiO2)
Post Processing
Electric Fields
E Field Scale:
3.2 MV cm
Smallest Triangles: 0.3nm edges 12

14. Carrier Concentrations in Fin (SiO2)
cm-3
cm-3 13

15. Gate Current Tunneling
Gate Metal
Oxide
Si Fin
Non-uniformity
Direct
Tunneling
Leakage
Defects/Traps
Trap-assisted
Tunneling Leakage IG
tox
Thin gate oxides:
High electric fields
Direct tunneling currents
Barrier for tunneling (CB offset) smaller for HfO2 than SiO2
Trap-assisted tunneling currents
Saraswat, Thin Dielectrics for MOS Gate 14

16. WKB Tunneling Ox Si Ox Si Ox Si 15 Ox Si
Tunneling, Dragica Vasileska and Gerhard Klimeck
Ox Si
Ox Si
Ox Si
Ox Si 15

17. Gate Tunneling Leakage Current
Direct tunneling through trapezoidal oxide barrier at low gate voltages/ thin oxides
For Vg=1V in saturation:
ID-on=661μA
ID-off=nA range
IG-tunnel=1.73μA
IG/ID increases for
smaller devices 16

18. Dielectric Breakdown Carrier tunneling can break weak oxide bonds
Material
EBD
SiO2
10 MV/cm
HfO2
6 MV/cm
Carrier tunneling can break weak oxide bonds
For tox=2nm, breakdown at VG=1.3V
SiO2 Breakdown
HfO2 Breakdown 17

19. Effect of Defects in FinFET Dielectric; Analyze Reliability and EMI Effects with DFT
Fin thickness: Tfin=25nm
Oxide thickness:
Tox = 1.6nm
Height: Hfin=75nm
Fin Substrate: BOX = Buried Oxide
Channel Length: Apprx. 14nm (not shown)
Rectangular geometry contains corners.
Nowak, et al, IEEE Cir&Dev Mag, p Jan/Feb 2004 18

20. Investigate Role of Defects in EMI
Oxide with Defect
Ideal Oxide
Defects reduce performance and most likely enhance vulnerability 19

21. This work focuses on NBTS degradation potentially due to OV hole traps
Effect of Defects on MOSFETs; High Voltage Bias Changes Threshold Voltage (Vt)
Positive shift in Vth following HT positive bias stress due to electron trapping.
Negative shift in Vth following HT negative bias stress due to hole trapping.
The degradation worsens over time!
This work focuses on NBTS degradation potentially due to OV hole traps
OV = Oxygen Vacancy
* Measurements by our collaborators at U.S. Army Research Lab,
Adelphi, MD. 20

22. Density Functional Theory: Use to Analyze
Schrodinger wave equation that accounts for all the electrons and nuclei in the system and their interactions.
Total wavefunction
The kinetic and potential energies are altered by quantum effects like Pauli’s exclusion – not quantifiable.
DFT provides a tractable accurate solution for the ground state eigenvalues (energy) and electron density.
Replaces the complicated interacting system Hamiltonian by a sum of non- interacting Hamiltonians.
Uses electron density (one function in space) as the fundamental property instead of ψtot. 21

23. DFT Shows Oxygen vacancy (OV) defects give rise to charge trapping centers
Structural and electronic properties of OVs in MOS oxide regions were studied.
Structures of OV in oxide regions:
Basic Low-energy Dimer,
High-energy forward-projected (fp),
High-energy back-projected (bp)
Upon hole capture, basic dimer spontaneously forms positive fp.
fp thermally transforms to bp.
Also, fp and bp are stable when neutral. 22

24. Transient modeling of OV hole trap activation under NBTS (contd..)
The time-dependent total concentration of activated hole traps (positive charges) is translated to voltage shift in negative direction.
Δ𝑉 𝑡 =− 𝑞 𝑁 𝑖=2 6 𝑥 𝑖 (𝑡) 𝐶
Simulated NBTS
Experimental
OV hole trap activation is a serious contributor to HTGB reliability degradation in 4H-SiC MOSFETs (from integrated modeling using DFT and rate equations) .
[1] A. J. Lelis et. al, IEEE T-ED, vol. 62, no.2, pp , 2015.
[2] M.A. Anders et.al., IIRW pp , Oct 23

25. Summary and Future
EMI can couple to micro and nano devices via PC Board traces.
MOS Gate Oxides are especially vulnerable to induced terminal voltages.
Created FEM solver for nonlinear Poisson equation in FinFET
Calculated Dielectric Breakdown Voltages and Tunneling Effects with Solver.
Oxides are very thin and can have defects (Oxygen Vacancies) which enhance vulnerability
Density Functional Theory plus related modeling tools calculates defect states on atomic level.
Transient Arrhenius type model developed that uses DFT QM Atomic Structure and State results to quantify charging.
Model correctly quantifies MOSFET threshold voltage shift due to gate voltage bias stress.
Future:
Add transient analysis to oxide field calculations
Investigate defects in HfO2 (new high K) gate dielectrics (Current work was SiO2) 24