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CS 3013 & CS 502 Summer 2006 Concurrency & Processes1 CS3013 & CS502 Operating Systems.

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Presentation on theme: "CS 3013 & CS 502 Summer 2006 Concurrency & Processes1 CS3013 & CS502 Operating Systems."— Presentation transcript:

1 CS 3013 & CS 502 Summer 2006 Concurrency & Processes1 CS3013 & CS502 Operating Systems

2 CS 3013 & CS 502 Summer 2006 Concurrency & Processes2 Thought experiment static int y = 0; int main(int argc, char **argv) { extern int y; y = y + 1; return y; }

3 CS 3013 & CS 502 Summer 2006 Concurrency & Processes3 Thought experiment static int y = 0; int main(int argc, char **argv) { extern int y; y = y + 1; return y; } Upon completion of main, y == 1

4 CS 3013 & CS 502 Summer 2006 Concurrency & Processes4 Program 1 int main(int argc, char **argv) { extern int y; y = y + 1; return y; } Program 2 int main2(int argc, char **argv) { extern int y; y = y - 1; return y; } Assuming programs run “in parallel,” what are possible values of y after both terminate? Thought experiment (continued) static int y = 0;

5 CS 3013 & CS 502 Summer 2006 Concurrency & Processes5 Fundamental Abstraction On (nearly) all computers, reading and writing operations of machine words can be considered as atomic Non-interruptible Appears to take zero time It either happens or it doesn’t Not in conflict with any other operation No other guarantees (unless we take extraordinary measures)

6 CS 3013 & CS 502 Summer 2006 Concurrency & Processes6 Definitions Definition: race condition When two or more concurrent activities are trying to change the same variable to different values Random outcome Critical Region (aka critical section) One or more fragments of code that modify the same data, such that at most one activity at a time may be executing anywhere in that set of fragments.

7 CS 3013 & CS 502 Summer 2006 Concurrency & Processes7 Tanenbaum, page 103 Synchronization – Critical Regions

8 CS 3013 & CS 502 Summer 2006 Concurrency & Processes8 Class Discussion How do we keep multiple computations from being in a critical region at the same time? Especially when number of computations is > 2 Remembering that read and write operations are atomic

9 CS 3013 & CS 502 Summer 2006 Concurrency & Processes9 Approaches to controlling access to a critical section Without OS assistance — Locking variables & busy waiting Peterson’s solution (p. 105) Atomic read-modify-write – e.g. Test & Set With OS assistance on single processor Disable interrupts Semaphores Mutex (Mutual Exclusion – specialized semaphore) Monitors Barrier synchronization What about multiple processors? Shared memory Non-shared memory

10 CS 3013 & CS 502 Summer 2006 Concurrency & Processes10 Requirements – Controlling Access to a Critical Section –Symmetrical among n computations –No assumption about relative speeds –A stoppage outside critical section does not lead to potential blocking of others –No starvation — i.e. no combination of timings that would cause a computation to wait forever to enter its critical section

11 CS 3013 & CS 502 Summer 2006 Concurrency & Processes11 Non-solution static int turn = 0; Computation 1 while (TRUE) { while (turn !=0) /*loop*/; critical_region(); turn = 1; noncritical_region1(); }; Computation 2 while (TRUE) { while (turn !=1) /*loop*/; critical_region(); turn = 0; noncritical_region2(); };

12 CS 3013 & CS 502 Summer 2006 Concurrency & Processes12 Non-solution static int turn = 0; Computation 1 while (TRUE) { while (turn !=0) /*loop*/; critical_region(); turn = 1; noncritical_region1(); }; Computation 2 while (TRUE) { while (turn !=1) /*loop*/; critical_region(); turn = 0; noncritical_region2(); }; What is wrong with this approach?

13 CS 3013 & CS 502 Summer 2006 Concurrency & Processes13 Peterson’s solution (2 computations) static int turn = 0; static int interested[2]; void enter_region(int process) { int other = 1 - process; interested[process] = TRUE; turn = process; while (turn == process && interested[other] == TRUE) /*loop*/; }; void leave_region(int process) { interested[process] = FALSE; };

14 CS 3013 & CS 502 Summer 2006 Concurrency & Processes14 Homework Assignment Can Peterson’s solution be generalized to more than 2 concurrent computations? A: Read Tanenbaum, §2.3 B: Read Dijkstra, “Solution to a Problem of Concurrent Program Control” (pdf)pdf C: Class discussion next week.

15 CS 3013 & CS 502 Summer 2006 Concurrency & Processes15 Test & Set Instruction (built into CPU hardware) static int lock = 0; extern int TestAndSet(int &i); /* sets the value of i to 1 and returns the previous value of i. */ void enter_region(int &lock) { while (TestAndSet(lock) == 1) /* loop */ ; }; void leave_region(int &lock) { lock = 0; };

16 CS 3013 & CS 502 Summer 2006 Concurrency & Processes16 Test & Set Instruction (built into CPU hardware) static int lock = 0; extern int TestAndSet(int &i); /* sets the value of i to 1 and returns the previous value of i. */ void enter_region(int &lock) { while (TestAndSet(lock) == 1) /* loop */ ; }; void leave_region(int &lock) { lock = 0; }; What is wrong with this solution?

17 CS 3013 & CS 502 Summer 2006 Concurrency & Processes17 Variations Compare & Swap (a, b) temp = b b = a a = temp … A whole mathematical theory about efficacy of these operations All require extraordinary circuitry in processor memory, and bus to implement atomically

18 CS 3013 & CS 502 Summer 2006 Concurrency & Processes18 Different Approach Use OS to help Implement an abstraction:– A data type called semaphore with integer values. An operation wait_s(semaphore &s) such that –if s > 0, atomically decrement s and proceed. –if s <= 0, block the computation until some other computation executes post_s(s). An operation post_s(semaphore &s):– –Atomically increment s; if one or more computations are blocked on s, allow precisely one of them to unblock and proceed.

19 CS 3013 & CS 502 Summer 2006 Concurrency & Processes19 Critical Section control with Semaphore static semaphore mutex = 1; Computation 1 while (TRUE) { wait_s(mutex); critical_region(); post_s(mutex); noncritical_region1(); }; Computation 2 while (TRUE) { wait_s(mutex); critical_region(); post_s(mutex); noncritical_region2(); };

20 CS 3013 & CS 502 Summer 2006 Concurrency & Processes20 Semaphores – History Introduced by E. Dijkstra in 1965. wait_s() was called P() Initial letter of a Dutch word meaning “test” post_s() was called V() Initial letter of a Dutch word meaning “increase”

21 CS 3013 & CS 502 Summer 2006 Concurrency & Processes21 Abstractions The semaphore is an example of a new and powerful abstraction defined by the OS I.e., a data type and some operations that add a capability that was not in the underlying hardware or system. Once available, any program can use this abstraction to control critical sections and more powerful forms of synchronization among computations.

22 CS 3013 & CS 502 Summer 2006 Concurrency & Processes22 Processes

23 CS 3013 & CS 502 Summer 2006 Concurrency & Processes23 Background – Interrupts A mechanism in (nearly) all computers by which a running program can be suspended in order to cause processor to do something else Two kinds:– Traps – synchronous, caused by running program –Deliberate: e.g., system call –Error: divide by zero Interrupts – asynchronous, spawned by some other concurrent activity or device. Essential to the usefulness of computing systems

24 CS 3013 & CS 502 Summer 2006 Concurrency & Processes24 Hardware Interrupt Mechanism Upon receipt of electronic signal, the processor Saves current PSW to fixed location Loads new PSW from fixed location PSW — Program Status Word Program counter Condition code bits (comparison results) Interrupt enable/disable bits Other control and mode information –E.g., privilege level, access to special instructions, etc. Occurs between machine instructions An abstraction in modern processors (see Tanenbaum, §5.1.5)

25 CS 3013 & CS 502 Summer 2006 Concurrency & Processes25 Interrupt Handler /* Enter with interrupts disabled */ Save registers of interrupted computation Load registers needed by handler Examine cause of interrupt Take appropriate action (brief) Reload registers of interrupted computation Reload interrupted PSW and re-enable interrupts or Load registers of another computation Load its PSW and re-enable interrupts

26 CS 3013 & CS 502 Summer 2006 Concurrency & Processes26 Requirements of interrupt handlers Fast Avoid possibilities of interminable waits Must not count on correctness of interrupted computation … More challenging on multiprocessor systems

27 CS 3013 & CS 502 Summer 2006 Concurrency & Processes27 “process” (with a small “p”) Definition: A particular execution of a program. Requires time, space, and (perhaps) other resources Can be Interrupted Suspended Blocked Unblocked Started or continued Fundamental abstraction of all operating systems Also known as thread (of control), task, job, etc. Note: a Unix/Windows “Process” is a heavyweight concept with more implications than this simple definition

28 CS 3013 & CS 502 Summer 2006 Concurrency & Processes28 State information of a process PSW (program status word) Program counter Condition codes Registers, stack pointer, etc. Whatever hardware resources needed to compute Control information for OS Owner, privilege level, priority, restrictions, etc. Other stuff …

29 CS 3013 & CS 502 Summer 2006 Concurrency & Processes29 Process and semaphore data structures class State { long int PSW; long int regs[R]; /*other stuff*/ } class PCB { PCB *next, prev, queue; State s; PCB (…); /*constructor*/ ~PCB(); /*destructor*/ } class Semaphore { int count; PCB *queue; friend wait_s(Semaphore &s); friend post_s(Semaphore &s); Semaphore(int initial); /*constructor*/ ~Semaphore(); /*destructor*/ }

30 CS 3013 & CS 502 Summer 2006 Concurrency & Processes30 Implementation Ready queue PCB Semaphore A count = 0 PCB Semaphore B count = 2

31 CS 3013 & CS 502 Summer 2006 Concurrency & Processes31 Implementation Action – dispatch a process to CPU Remove first PCB from ready queue Load registers and PSW Return from interrupt or trap Action – interrupt a process Save PSW and registers in PCB If not blocked, insert PCB into ReadyQueue (in some order) Take appropriate action Dispatch same or another process from ReadyQueue Ready queue PCB

32 CS 3013 & CS 502 Summer 2006 Concurrency & Processes32 Implementation Action – wait_s(Semaphore &s) Implement as a Trap (with interrupts disabled) if (s.count == 0) –Save registers and PSW in PCB –Queue PCB on s.queue –Dispatch next process on ReadyQueue else –s.count = s.count – 1; –Re-dispatch current process Ready queue PCB

33 CS 3013 & CS 502 Summer 2006 Concurrency & Processes33 Implementation Action – post_s(Semaphore &s) Implement as a Trap (with interrupts disabled) if (s.queue != null) –Save current process in ReadyQueue –Move first process on s.queue to ReadyQueue –Dispatch some process on ReadyQueue else –s.count = s.count + 1; –Re-dispatch current process Ready queue PCB Semaphore A count = 0 PCB

34 CS 3013 & CS 502 Summer 2006 Concurrency & Processes34 Device Interrupts Implemented as post_s to special semaphores Device-specific handling entrusted to device manager processes Very high priority Requests from application processes Implemented in device-specific routines Critical sections Buffers and variables shared with device managers

35 CS 3013 & CS 502 Summer 2006 Concurrency & Processes35 Timer interrupts Can be used to enforce “fair sharing” Current process goes back to ReadyQueue After other processes of equal or higher priority Simulates concurrent execution of multiple processes on same processor

36 CS 3013 & CS 502 Summer 2006 Concurrency & Processes36 Definition Context Switch — the act of switching from one process to another E.g., upon interrupt or block Not a big deal in simple systems and processors Very big deal in large systems such Unix and Windows Pentium 4

37 CS 3013 & CS 502 Summer 2006 Concurrency & Processes37 Complications for Multiple Processors Disabling interrupts is not sufficient for atomic operations Semaphore operations must themselves be implemented in critical sections Queuing and dequeuing PCB’s must also be implemented in critical sections Other control operations need protection These problems all have solutions but need deeper thought!

38 CS 3013 & CS 502 Summer 2006 Concurrency & Processes38 Summary Interrupts transparent to processes wait_s() and post_s() behave as if they are atomic Device handlers and all other OS services can be embedded in processes All processes behave as if concurrently executing Fundamental underpinning of all modern operations systems

39 CS 3013 & CS 502 Summer 2006 Concurrency & Processes39 Summary Homework: reading and extending Peterson’s solution to n > 2.

40 CS 3013 & CS 502 Summer 2006 Concurrency & Processes40 Break (next topic)


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