1. Performed by: Tomer Michaeli 052792769 Liav Cohen 301242509 Instructor: Shlomo Beer Gingold Cooperated with: המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering characterization of synchronizers and metastability and metastability Winter 2010 1

2. Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 Recent meta-stability measurements down to 65nm technologies indicated increase of MTBF (Mean Time Between Failures) with technology scaling. As opposed to those conclusions, later on-chip measurements on up to 65nm technologies showed degradation of MTBF with technology scaling [2].2 This project deals with off-chip measurements of Flip Flops (FF’s) parameters [1] and comparison to the on-chip measurements (in 65nm technology) [5].15 The FFs are included in the synchronizer circuits (synchronizers), hence the parameters have high importance in system reliability. The two main parameters that are calculated: Tw, (resolution time constant). Notice that is predominant since its effect on MTBF is exponential.

3. System Block Diagram and Description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5 Fd [Hz] Fc [Hz] synchronizer clock (Input) Data (TRIGGER) PC 3.125MHz \ 6.245MHz 6.25MHz Choosing one of the synchronization circuits : -regular FF -synchronizer 1 -synchronizer 2 F_data=(Fc-Fd)[Hz] Calculating the delay between clock rising to data rising by the scope Getting the measurements values from scope to PC by VEE program DSO80204B Scope Input TRIGGER

4. Measurements המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 Measurements were performed at Vdd=1.1V and room temperature.  2 DATA frequencies 3.125 [MHz] and 6.245 [MHz] were measured and clock frequency 6.25 [MHz]  Measurement period time: T=200 [sec] for each delay value.  Measurements were executed on 3 different chips  Calculating,by the scope, the delay between the DATA signal (synchronizer output) and the clock signal (Ch1-Ch2), which mean the delay between clock rising to the data stabilizing.  Getting the measurements values from the scope to PC by VEE program (with GPIB connection).

5. Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware Software 4 An oscilloscope that can create histograms FPGA board DLP daughter board. Signal generator Voltage regulator Test chip board PC, including Xillinx ISE, Visual Studio. MATLAB

6. References המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 6 1.Yaron Semiat and Ran Ginosar, ‘Timing Measurements of Synchronization Circuits’, Technion, Haifa, 2003. 2.Shlomo Beer Gingold, ‘Test Chip (Sinc_test_chip)’, Technion, Haifa. 3.Salomon beer,Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin and Avinoam Kolodny, 'The Devolution of synchronizers', Technion, Haifa, 2010. 4. Lindsay Kleeman & Antonio Cantoni, 'Metastable Behavior in Digital Systems', University of Newcastle, New South Wales, 1987. 5.Salomon Beer, Ran Ginosar, Michael Priel, Rostislav (Reuven) Dobkin and Avinoam Kolodny, 'An on-chip metastability measurement circuit to characterize synchronization behavior in 65nm', Technion, Haifa. 6.DLP Design, 'DLP-USB245M-G USB to FIFO Parallel Inetrface Module', 1605 Roma Lane, Allen TX 75013. 7. 'Xilinx University Program Virtex-ll Pro Development System', UG069, March 8,2005