1. Design Choices for SuperBelle P. Fischer, I. Peric, Ch. Kreidl, J. Kinzel Heidelberg University 1Design Choices for SuperBelle

2. Outline  Bumping constraints & consequences  Switcher  DCD 2Design Choices for SuperBelle

3. Philosophy  Must build a full detector in only 3 years 3Design Choices for SuperBelle  If possible, have ideas for better performance later Choose simple solution. Avoid risks Be ready to sacrifice performance for this

4. BUMPING

5. Bumping Constraints  Compare 3 possible ways to do the bumping: 1.Gold Studs 2.Buy chips with PbSn bumps or similar (possible for UMC via SPIL wafer bumping service, IBM,…) 3.Get everything done by company 5Design Choices for SuperBelle TechnoMin. pitch Bump pad Max. bumps Pressure / bump UBM Sensor Wafers Needed ReworkCostWho Au Stud100 70 (60) 400>30gno NoLow HD, (BN, HLL) Bumped Chips 15050 (?)  0yesNoYesMed HD, (BN, HLL) By vendor 5015  0yes YesHighIZM,…

6. Consequences  Keep bump pitch at 150µm  Keep bump pad size at >65µm (best 70µm)  Restrict #bumps per chip to ~400  Do not put anything under bump pads A test chip with structures under bumps has been submitted  Start another wafer with dummy structures for yield tests as soon as chip geometries are fixed  Make tests with large number of gold studs (500)  Start development of UBM process @ HLL 6Design Choices for SuperBelle

7. SWITCHER

8. BelleSwitcher: What has changed?  What has changed w.r.t. ILC? Pixels are larger in z  Less channels per z needed Pixels are wider in phi  blocks of 4  even less pixels needed  Only ~ 128 x 2 switcher channels for gate, clear required Furthermore, we run continuously. Must decrease power  Discuss 3 possible control options: 1.Sequencer (as in Switcher 3) 2.Shift register (as in Switcher 2) 3.Multiplexer  Assume both voltages are switched within one chip.  For HV Switch choice: See later 8Design Choices for SuperBelle

9. Boundary conditions  128 rows on half module  Module height ~ 10cm  12 µm trace pitch  For two chips of 64 x 2 channels: Routing all signals on M1 requires width of 1.5mm for traces Less if M2 is used 32 control signals in M2 would need 400µm 9Design Choices for SuperBelle 2 x 64 traces x 12 µm = 1536µm

10. 1. Sequencer  Has been introduced in Switcher 3 Can skip bad rows Can read some parts more frequently Can switch between programs (ROI readout,…)  Pros: Very nice, flexible design (but what for?) Small number of control lines Exists  Cons: Complicated circuit (but exists) Still needs work to get floating logic SEU sensitive (-> Error bit, Hamming correction,… = work) Overhead makes sense only for large chips (>= 64 channels) A bit tricky to know that no clocks got lost… 10Design Choices for SuperBelle

11. 2. Multiplexer  MUX with Enable line  Requires some control in DHP (minimum: just a counter) 11Design Choices for SuperBelle Switch ClearHi/Lo Level Shift Clear StrP/N vddf / gndf Gate StrP/N Switch GateHi/Lo Level Shift En6-En0 P/N 7x VDDA / GNDAWriteMonitor

12. 2. Multiplexer  Pros: Very Simple NO storage (except few bias bits)  no SEU problems Arbitrary sequences are possible (via Sequencer in DHP) Can do arbitrarily small chips Minimum Power (in digital part)  Cons: ‘Larger’ number of (Address) lines: 7 differential lines 12Design Choices for SuperBelle

13. Pins Multiplexer  7x2En  6:0  Enable  2x2Strobe Clear and Gate  2gndf, vddfDigital  2 x 2VLo, Vhifor Gate and Clear  2VDDA, GNDA??? Needed for HV part  1Monitor, for test only  ~3Slow control interface, reset  ~30total 13Design Choices for SuperBelle

14. 3. Shift register  Re-inject serial input at every pass  Requires some control in DHP (inject every 128 clocks, monitor serial output for SEU)  Pros: Simple Only transient storage Minimum number of control lines (SERIN, SEROUT(for monitor), CLK, RESET)  Cons: Sequences limited. Cannot skip rows 14Design Choices for SuperBelle

15. More questions  Where to generate strobes for gate & clear? In switchers from a reference clock (  strobes may vary slightly between rows) In DHP (  strobes may vary slightly between sides / modules) Externally: Best control. Only two extra differential lines!  How many channels per chip 1281 chipfanin too wide 642 chipswidth of fanin is 1.5 mm (one metal) / 0.8 mm 32 4 chipsfanin 0.8mm / 0.4mm 168 chipstoo many chips  Do we need decoupling? Will put as much On-chip cap as possible. This may be enough May require a few SMD caps 15Design Choices for SuperBelle

16. More questions  RC of sensor traces (dominated by trace, independent of W): Worst case model: R = L / W x 30m  C =  x  0 x W x L / d  = ½ RC =  x L 2 x 0.27 x 10 -9 ns / µm / d  = 4, d = 1µm = 6ns for L=7.5 cm  This is already at the limit for timing critical signals (strobes / clock)  This indicates that we should use M2 for vertical traces (lower capacitance) 16Design Choices for SuperBelle

17. HV part  Ivan has improved new ‚SWITCHER4‘ HV part by changing layout of enclosed ‚rad hard HV transistor‘ 17Design Choices for SuperBelle 50V maximal voltage Floating logic Two outputs/channel Rad hard Relative fast Break before make  0,3,17,20V supply/channel – 3V and 17V generated intenally

18. D G SB p- sub p- n- n+p+ D G S Annular DNMOS

19. logic out 20V 17V 3V 0V in Simplified Schematic

20. Switcher4 Test Chip - 64 channels - Clear and gate output - Pin compatible with switcher 2 - LVDS inputs - Shift register - Voltage regulators on chip

21. switches between 0 and 15 Vswitches between 15 and 0 V First Quick Measurements

22. switches between 10 and 0 Vswitches between 0 and 10 V Sw4 measurements Some more

23. More.. switches between +7 and -7 Vswitches between +15 and +5 V

24. Sw4 measurements Switching between 30V and 0V

25. Next steps  Decide on control mechanism  Try real layouts to solve Fanin – Control – Chip Geometry choice  Try to keep balcony as small as possible (<2mm)  Irradiate HV switch in KA (setup ready) 25Design Choices for SuperBelle

26. DCD

27. New geometry  Goals: Go to larger bump pitch (for possible PnSn..) Make gap between chips larger to accommodate errors in chip cutting (as observed in MPWs) Make Y a multiple of 4 (simplify readout, Request by Hans)  Proposed Geometry: 10 pixels in X, pitch = 150µm 16 pixels in Y, pitch = 150µm 27Design Choices for SuperBelle

28. Routing for DCD with 10 x 16 pixels of (150µm) 2  Number of pixels:160 = 10(x) x 16 (y)  Width of sensor part:160 x 12.5µm = 2000µm  Bump pad width70 µm  Space for traces2000µm – 10 x 70µm = 1300µm  Number of traces1300µm / 12µm = 108 > 160/2 – OK  Nominal gap2000µm – 1525µm = 475 µm – OK 28Design Choices for SuperBelle 2000 µm 70 µm

29. Pad arrangement on chip  Chip Geometry: 3x1 MINIASICs = 1525 µm x 5000 µm  Have only analog stuff in upper pixels  Move digital stuff to the bottom Synthesis Use radiation hard library for a start 29Design Choices for SuperBelle 10 x 16 ANALOG parts (bump + cascode + current memory + ADC) Analog Power pads Digital Power Pads Digital Outputs Control DIGITAL STUFF

30. Readout options  Goals: Be prepared for large current variation in matrix Common mode subtraction (?) Faster readout without double sampling (?) 1.Increase current range of current subtraction cell Conceptually simple Costs area 2.Increase dynamic range (= #bits) of ADC Challenging Very flexible Readout without double sampling possible 3.DAC to subtract coarse current Needs memory -> SEU issue Readout without double sampling possible 30Design Choices for SuperBelle

31. 31 Radiation Hard Standard cells  Cell height: 7.44µm  Available cells so far: INV(Inverter) NAND2(2-Input NAND) NOR2(2-Input NOR) NOR3(3-Input NOR) MUX2(2-Input Multiplexer) XOR(Exclusive OR) GTINV(Gated Inverter) TGATE(Transmission Gate) DL(D Latch) RSFF(Set-Reset-FlipFlop) DFF(D-FlipFlop) DFRS(D-FlipFlop with Set/Reset) FEED(Core Filler Cell) ENDCAP(Row Termination Cell)  Mixed mode support: NWELL and substrate connected to separate nets

32. 32 Standard cell verification  A test design with several synthesized & automatically placed and routed designs has been submitted  All designs work as expected

33. Plans  Freeze Geometry  Choose FE concept  Submit 3x1 MiniASIC with bumps  Submit smaller chip with wire bond pads 33Design Choices for SuperBelle

34. Thank you 34Design Choices for SuperBelle

35. UMC018: Possible Chip Dimensions  Submissions via Europractice: Full 5 x 5 mm2 runs every 2 month, <14.5k€ MiniASIC with blocks of (1.525mm)2 every 4 months, ~1.8k€ per block ~2.5 months delivery Cost break even at 6 MiniASIC Blocks !  Scribe Line: Taking the possible MiniASIC dimensions (see figure) the scribe line + seal ring seems to be <=190µm Dicing is obviously done with a pitch of 1525µm + 190µm We must therefore assume that the real chip size is (190µm – blade width) more than expected... Design Choices for SuperBelle 4960 µ 1525 µ 3240 µ 3240 µ – 2 x 1525 µ = 190 µ 35

36. Optimize for Phi resolution  We always hit two pixels in z   bricking pixels in Phi doubles resolution in Phi 36Design Choices for SuperBelle z DCD Switcher z=0

37. Estimation of routing requirements (Switcher@End)  Assume 600 pixels in z 200 pixels in Phi Pixel width = 50µm Grouping of N pixels (N~4)  This gives Module width = 200 x 50µm = 10.000 µm we have 200 * N drain lines we need 600 / N x 2 = 1200 / N gate + clear lines in total Total number of lines (drain + clear + gate) is 200 (N + 6 / N) The pitch p of these lines is 50 µm / (N + 6 / N) This has a (flat) minimum for N = sqrt(6) = 2.5.. N=2: p = 10µm, 300 clear, 300 gate, 400 drain N=4: p = 9µm, 150 clear, 150 gate, 800 drain  For comparison: Normal Layout with N=4 requires p=12.5µm 37Design Choices for SuperBelle

38. POWERPOWER POWERPOWER Possible Switcher Geometry (assume 16 x 2) 38Design Choices for SuperBelle A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B A B B Clear / Gate to Matrix A B B A B A B B A B B A B A B B A ~8 x 160µm ~ 1.4mm Addresses, Strobes Power B B

39. POWERPOWER POWERPOWER Alternative Switcher Geometry (assume 16 x 2) 39Design Choices for SuperBelle ABAB ABAB ABAB ABAB ABAB ABAB ABAB ABAB B B B B B B B B ABABB ABABB Digital signals on right side Clear / Gate to Matrix