1. Paola TDAQ 13-09-2010 1 FTK STATUS (valid for both Option A & B) Paola Giannetti for the FTK collaboration  Work done for each milestone since the TDAQ approval o Software: Architecture study, improvement, understanding o Hardware advancement  For L2 triggers: as soon as FTK is approved, we will need L2 algo. update to profit of FTK early-available tracks (2013) 1. Optimize b, tau, and muon efficiency using tracks at the beginning of LVL2 2.New triggers to increase efficiency and searched phase space (2 examples) EM isolation only 60 and 120 MeV THs 60 MeV 120 MeV Pythia W→  2,6  10 33 (a)Use tracks before calorimeter if convenient (i.e. isolation) (b)Use more complex b-tag algos→large overlap with offline b-tag (c)Use new tau-tag algos→large overlap with offline tau-tag (d)What to do at EF when L2 selects high quality bs & taus?

2. Paola TDAQ 13-09-2010 2 t0= Atlas approval of TDAQ action → funds become available 1.Performance vs. Min P T at 3×10 34 on going3 months 2.Single track efficiency vs. beam offset done3 months 3.Investigate adding XON/XOFF to new HOLA done 4 months 4.Improve efficiency in the barrel/forward interface region advanced6 months 5.Performance versus dead channel fraction (wildcard option) just started 6 months 6.TSP simulation including varying-resolution pattern banks advanced 8 months 7.Optimization of clustering at 3×10 34 just started 9 months 8.Production readiness review for dual-output HOLA expected June 1112 months 9.Specify system size for 3×10 33, 1×10 34, and 3×10 34 on going12 months 10.Prototype in lab (EDRO & AM); start TDAQ integration on going 12 months 11.Handling FTK errors in level-2 and Event Filter 14 months 12.Studies with real ATLAS data just started 18 months 13.Select baseline design 18 months 14.Integrate FTKSim into ATHENA 18 months 15.TDR including tests of prototype boards 24 months Milestones associated to the TP

3. Paola TDAQ 13-09-2010 3 Milestone #1: Performance vs. Min PT at 3×10^34 Systematic studies started for the Min P T 1 - 1,5 - 2 GeV (Option B). 45 k 230 k 2,9 k 57 k 83 k Reduction of factors 2-3-4 0 2 4 6 8 10 12 14 16 18 20 PT [1/GeV] Guido Volpi - Pisa Electron reconstruction compared to other particles @ 3×10^34 : they are not much worse than Muons & Pions NEXT: test performance losses on b and tau tagging, track- based isolation etc. etc. using offline analysis. Anton Kapliy & Yangyang Cheng Chigaco 1 st STEP 2 nd STEP

4. Paola TDAQ 13-09-2010 4 Milestone #2: Single track efficiency vs. beam offset Efficiency vs offset – used bank: 11L, 50x64x144, 100K events/point Jordan Webster - Chicago Typical x misalignment < 200  m Typical z misalignment < 10 mm d0 resolution 0,998 1 1 0,992

5. Paola TDAQ 13-09-2010 5 Milestone #3: Investigate adding XON/XOFF to new HOLA Anton Kapliy & Fukun Tang - Chicago Proposal for implementing flow control in the FTK fiber approved by S. Haas @Cern Preliminary studies have shown we can use the cheapest Cyclone IV GX FPGA to: 1.host the modified LSC (link source card) firmware 2.directly use its internal transceivers/receivers (dropping the external SERDES). Anton: modify the firmware to allow for flow control from FTK side Fukun: will soon start the new board layout. We are on track for a fully tested prototype by June, 2011, with a CERN production readiness review shortly after that. Production & testing in time for installation during the 2012 shutdown.

6. Paola TDAQ 13-09-2010 6 Milestone #4: Improve  in the barrel/forward interface region Missing gap SCT pairs Missing any SCT pairs WH 10^34 Joe Tuggle - Chicago 1 ring of modules (all  ) at the larger  in the barrel and 1 disk at the smallest  in the forw. in the layers 10-11 allowed to be missing

7. Paola TDAQ 13-09-2010 7 Milestone #6: TSP simulation & varying-resolution pattern banks Guido Volpi & Roberto Vitillo - Pisa Depth 0 Depth 1 Depth 2 PARENT PATTERN FAT ROAD Thin ROAD AM resolution TSP resolution We do have now a structured “pattern bank”, where each thin road is connected to its parent pattern in FTKsim. Ongoing tests for TSP algo after the RoadFinder (AMsim) in FTKsim; we have studied the bank composition and AM FAKE roads. AM Fake road is a AM matched pattern whose kids do not match the event Low probability to fire AM patterns: few kids (1 or 2): big advantage to test it at TSP resolution! All blank Half-SS can fire @ AM level as fakes while @ TSP level the fake has good probability to be deleted LOW coverage patterns High probability to fire AM patterns (symmetric): many kids (up to 20 or more): no advantage to test it at TSP resolution! More than one kid can fire @ TSP level. Low probability to be a fake AM road HIGH coverage patterns KID PATTERN @Depth 0 PARENT @Depth 1

8. Paola TDAQ 13-09-2010 8 We can use don’t care on the least significant bit when we want to test the pattern layer @ AM resolution or use all the bits to test it @ TSP resolution Test of AM patterns: 1.all single kid patterns @ TSP resolution 2.For all few kid patterns use don’t care only for layers where both Half-SS are used by kids AM resolution (don’t care ) TSP resolution to exclude the right half in these layers Guido Volpi & Roberto Vitillo - Pisa All AM roads AM roads with at least 1 matched kid Fake AM roads # of kids WH @10 34 How to implement “variable resolution” in the AMchip AM pattern distribution vs Number of kids Majority of patterns with a single Kid TSP bank SS sizes: 48 (pix  ) – 40 (SCT) – 72 (pix z) AM bank SS sizes: 96 (pix  ) – 80 (SCT) – 72 (pix z) 2,8 M patterns in AM barrel 8 Mpatterns in TSP barrel AM & TSP Pattern Bank for 23 ev. pileup # of kids

9. Paola TDAQ 13-09-2010 9 Milestone #9: Specify system size..1×10 34 and 3×10 33 Concentrate now on 2013-2015 (17-19 pile-up events) 2020 comes much later and will profit of a very advanced technology……. Sim with 75 pile-up events after 2020! 17,6 pile-up ev. @2.6 10 33 19,0 pile-up ev. @ 10 34

10. Paola TDAQ 13-09-2010 10 Using the variable resolution in a new AM chip for 10 34 WH events @10**34 (# of pile-up events = 23) Banks coverage ~ 95% 8.0 MPat @TSP → 2,80 MPat @ AM level (35%) per region (barrel only) 20 MPat @ TSP → 7 MPat @ AM level (35%) per region (all detector) Using TSP resolution in the AM bank for AM patterns with 1,2,3 kids: 3600 goes down to 1325 roads/AMboard → gaining a factor ~ 3! For a full detector FTK: less than 4000 roads/AMboard @AM out with a limit of 8000. less than 2000 roads/AMboard @TSP out with a limit of 4000. Guido Volpi & Roberto Vitillo - Pisa FTK Demonstrator with old chip, barrel only: running now on 17,6 pile- up events to understand DATA FLOW → however we consider it a test, It is not necessary to have large margins for 2013. Even a small AMchip (12 mm 2 ) @ 65 nm (MPW 80 k€) with variable resolution implemented, could do it, even without the TSP. Very low consumption DATA FLOW (Option A) assuming 16 AMboards in a core crate (numbers are for barrel only – a factor ~2,5 has to be applied for “all detector”): 3600 roads/AMboard of which 733 have a kid match at TSP level → 80% fakes

11. Paola TDAQ 13-09-2010 11 Milestone #10: Prototype in lab (EDRO & AM);TDAQ integration LAMB Standard cell chip FPGA for Roads P3 serial LVDS Control FPGA for SS Input Board Power consumption: 230 W @ 1,8 V today @ 1V Phase 1 → 128 A today → 230 A Phase 1 Fast and dense connectors Thin powerful - FPGAs Prototype Crate able to provide 230 W Cooling tests – Rack design 4 48 V→ 1,8 -1,2 V DC – DC converters 40-50 A output M. Piendibene Pisa Stabile-Andreani Milano A. Lanza Pavia Power/rack ~ 15 kW

12. Paola TDAQ 13-09-2010 12 Vertical Slice plan in Bologna: Bologna (EDRO) - Pisa (AMBoard) - Frascati (pixel clustering ) – Milano-Pavia (TSP-AMboard) Pixel clust. Fibers PC + Pseudo Hola Pixels Fired channels DO Roads + hits S-link SLink to PC or to other HW pieces (TSP)? A. Annovi M. Beretta LNF

13. Paola TDAQ 13-09-2010 13 180 nm 90 nm NEXT YEAR – MAY BE MARCH Mini-asic COULD be 90 or 65 nm THE AMCHIP04 PROTOTYPE Design: L.Sartori (Ferrara) M.Beretta (LNF) E. Bossini, F. Crescioli, I.Sacco (Pisa) Test: A.Lanza (Pavia) 90 nm miniasic

14. Paola TDAQ 13-09-2010 14 How to use FTK – new L1 & HLT selections - a couple of examples B S ->  ( x3 using soft second  ) B s  IP  ) Bs mass F.Crescioli-Pisa Athena + FTKsim Bs→  IEEE Trans. Nucl. Sci. 55, 145 (2008) LVL1: single  (Pt>6 GeV) LVL2 II  = track Pt>2,3,4,5,6 GeV II  i.p. (μ)>100um i. p. (Bs)<100um 4.8 GeV < M(μμ) < 6 GeV 30 fb-1 II  Pt>6 GeV 66 Bs ev. (|η|<1) 178 Bs ev. (|η|<2.5) II  Pt>3 GeV 230 Bs ev. (|η|<1) 546 Bs ev. (|η|<2.5|) LVL2 Backg. (bb in QCD – Pythia) Rate II  Pt>3 GeV O(10Hz)  Hadronic B Decay B PHYSICS: @LVL2: look for 1 track or more with i.p.>100  m and search 2-track or multi-track B decays

15. Paola TDAQ 13-09-2010 15 S/√B ~ 23 (30 fb -1 2014) Learn about low Mass peaks: Z→bb, Z → tau tau ATL-COM-PHYS-2004-053 I.Vivarelli- ATLFast Z→bb LVL1: 3 jets Pt>80, 30, 30 GeV LVL2 tag 2 b-jet OR 2 tau-Jet min < Mbb or Mvis < max OR LVL1: 1 soft  (Pt>6 GeV) 2 soft jets Pt>25 GeV OR 4 soft jets for Hbb,Htt… LVL2 tag 2 b-jet or 2 tau-Jet OR 3 b-jet min < Mbb < max IEEE Trans. Nucl. Sci. 51, 391 (2004) ATL-COM-DAQ-2002-022 b (or tau) Leading Jet (PT>80 GeV) Boosted Z→ bb Mbb GeV QCD bb background Trigger bias

16. Paola TDAQ 13-09-2010 16 Conclusions The LHC schedule is more clear: we will have 75 pile-up events in 2021! The new LHC schedule + “variable resolution pattern” results favors a new 65 nm AM chip implementing the new features soon, possibly being sufficient up to 2019 (42 pile-up events)+ a new version for 2021 (above 75 pile-up events) A lot of work has been done, much more is needed – we need interaction with the TDAQ for HLT selections It is important to measure on data the background rates & update the L2 – EF selections