1. © 2008, Renesas Technology America, Inc., All Rights Reserved 1 Course Introduction Purpose  This training course provides additional details about the CPU architecture of the MCUs in the M16C/2x and M16C/6x series. Objectives  Understand the instruction set and addressing modes.  Learn about Near and Far memory locations.  Discover specialized instructions in the CISC core that reduce code size and increase system performance. Content  22 pages  4 questions Learning Time  33 minutes

2. © 2008, Renesas Technology America, Inc., All Rights Reserved 2 Format of Instructions Example: MOV.W:GR0, R1 MOV.size.length:formatsrc, dest Op-code Mnemonic Size Specifier Jump-distance Specifier Format Specifier OperationOperand OperationOperand

3. © 2008, Renesas Technology America, Inc., All Rights Reserved Memory-Memory Operation M16C Memory-Memory Operation Register-register, register-memory, and memory-memory operations are available. Register-memory operation is available. 4-byte 6-byte RAM1 RAM2 Reg + RAM1 RAM2 LDA Reg, RAM1 AND Reg, RAM2 STA Reg, RAM2 AND.B RAM1[SB], RAM2[SB] 1 2 3 1 2 3 1 Load-Store PUSH Reg Pop Reg -- + 1

4. © 2008, Renesas Technology America, Inc., All Rights Reserved Read-Modify-Write Operation M16C Read-Modify-Write Operation LDA Port1, Reg AND #7, Reg STA Reg, Port1 AND.B #7, Port1 1 2 3 1 Typical MCU Operation If an interrupt occurs between instruction 1 and instruction 3, the value in Port1 could be changed by another function prior to data being written back. Since this is a single instruction, an interrupt will not be accepted until the instruction is completed. Thus, another function won’t be able to modify the port content.

6. © 2008, Renesas Technology America, Inc., All Rights Reserved 6 Instruction Set Types of OperationsInstructions Data Transfer (14) MOV,MOVA,PUSH,PUSHM,PUSHA,POP,POPM,LDE, STE,MOVDir,XCHG,STZ,STNZ,STZX Arithmetic (21) ADD,ADC,ADCF,SUB,SBB,MUL,MULUU, DIV,DIVU,DIVX,DADD,DADC.DSUB,DSBB, INC,DEC,RMPA,CMP,ABS,EXTS,NEG Shift/Logic (10) AND,OR,XOR,NOT,TST,SHL,SHA,ROT,RORC,ROLC Branch/Jump (10) JMP,JCnd,JMPI,JMPS,JSR,JSRI,JSRS,RTS,ADJNZ, SBJNZ Bit Manipulation (14) BCLR,BSET,BNOT,BTST,BNTST,BAND,BNAND, BOR,BNOR,BXOR,BXNOR,BCmd,BTSTS,BTSTC String Instructions (3) SMOVF,SMOVB,SSTR Control/ Other Instructions (19) LDC,STC,LDINTB,LDIPL,PUSHC,POPC,FSET,FCLR LDCTX,STCTX,ENTER,EXITD,BRK,REIT,INT,INTO, UND,WAIT,NOP

7. © 2008, Renesas Technology America, Inc., All Rights Reserved 7 Addressing Modes Operands are 16 or 20-bit addresses.abs16,abs20Absolute Pointer is formed by value in SP register plus signed displacement. dsp:8[SP]SP Relative Pointer is formed by value in FB register plus signed displacement. dsp:8[FB]FB Relative SymbolAddressing Mode Jump commandsProgram-Counter Relative (special addressing mode) Pointer is formed by value in SB register plus unsigned displacement. dsp:8[SB] dsp:16[SB] SB Relative Same as Address Register Indirect, but with an offset value added to contents of register. dsp:8[An] dsp:16[An] dsp:20[An] Address Register Relative Pointer is formed using value in register indicated in operand. [An]Address Register Indirect Operand is register to work on.RnRegister Direct Operands are data to work with.#imm:8/16Immediate Comment

8. © 2008, Renesas Technology America, Inc., All Rights Reserved 8 Far and Near Memory All address registers are 16 bits wide in the M16C CPU core. MOV instructions can only access Near memory (first 64KB).  MOV.B [A0],-1H[FB]  MOV.W -1H[FB],R0 LDE and STE instructions are used to access Far memory (addresses outside the first 64KB). Extended instructions use a 20-bit operand, or a 20-bit operand plus address register, to access total memory area.  LDE.B #D0000H[A0],422H  LDE.W #D0000H[A0],R0  STE.B R0, #D0000H Extended instructions can also use A1A0 combined to form the address.  STE.W 422H, [A1A0]

9. © 2008, Renesas Technology America, Inc., All Rights Reserved High-Speed Operations There are 10,222 combinations of instructions and addressing modes for the M16C CPU core. 10.0% 20.0% 30.0% 40.0% 50.0% 60.0% 0.0% 10.0% 20.0% 30.0% 40.0% 60.0% 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7cycle 8 cycle 9 cycle 10 cycle 11cycle more 2.1% 18.0% 50.8% 11.3% 3.3% 3.0% 4.2% 2.4% 3.2% 0.2% 1.4% 50.0% 0.0%

11. © 2008, Renesas Technology America, Inc., All Rights Reserved 11 Specialized Instructions  CISC cores have specialized instructions for common tasks that increase the efficiency of the MCU in typical embedded applications.  Some of the special instructions that the M16C devices provide are: − Multiply − Divide − Bit Manipulation − String Move Forward − ENTER/EXITD − PUSHM/POPM − RMPA − SMOVF

12. © 2008, Renesas Technology America, Inc., All Rights Reserved 12 Multiply Instruction MUL.sizesrc, dest dest x src dest ROL/ROROH/R1R1L/R2R1H/R3 A0/A0A1/A1[A0][A1] dsp:8[A0]dsp:8[A1]dsp:8[SB]dsp:8[FB] dsp:16[A0]dsp:16[A1]dsp:16[SB]abs16 #IMM src ROL/ROR1R1L A0/A0[A0][A1] dsp:8[A0]dsp:8[A1]dsp:8[SB]dsp:8[FB] dsp:16[A0]dsp:16[A1]dsp:16[SB]abs16 dest If you select (.W) for the size specifier, then src and dest both are operated on in 16 bits and the result is stored in 32 bits. If you specified R0, R1, or A0 for dest, then the result is stored in R2R0, R3R1, or A1A0 accordingly. Examples MUL.BA0, ROL MUL.W#3, R0 MUL.BR0L, R1L MUL.WR0, [A0] Multiplies lower byte of A0 and lower byte of R0 and stores result R0 (16 bits). Multiplies 16 bit R0 by 3 and stores result R2R0 (32 bits). Multiplies lower bytes of R0 and R1 and stores the result in R1. Multiplies value in R0 with value in memory pointed to by A0 and stores the 32-bit result in the location pointed to by A0. If you select (.B) for the size specifier and the source is an address register, the operation is performed on the address register’s eight low-order bits.

13. © 2008, Renesas Technology America, Inc., All Rights Reserved 13 Divide Instruction DIV.size src R2R0 ÷ src R0 (quotient), R2 (remainder) ROL/ROROH/R1R1L/R2R1H/R3 A0/A0A1/A1[A0][A1] dsp:8[A0]dsp:8[A1]dsp:8[SB]dsp:8[FB] dsp:16[A0]dsp:16[A1]dsp:16[SB]abs16 #IMM src If you select (.B) for the size specifier, Examples DIV.B A0 DIV.W A1 DIV.B -2H[FB] DIV.W -2H[FB] R0 ÷ src R0L (quotient), R0H (remainder) Divides value in R0 by lower byte of A0; R0L is quotient and R0H is remainder. If you select (.B) for the size specifier and source is address register, the operation is performed on the address register’s eight low-order bits. Divides value in R2R0 by word in A1; R0 is quotient and R2 is remainder. Divides R0 by byte in memory (FB register -2); R0L is quotient and R0H is remainder. Divides R2R0 by word in memory (FB register -2); R0 is quotient and R2 is remainder. If you select (.W) for the size specifier,

14. © 2008, Renesas Technology America, Inc., All Rights Reserved 14 Bit Manipulation Instruction Operation BSET 42,RAM 76543210 4746454443424140 15141312111098 b0b7 RAM RAM+1 RAM+5 Example BCLR 3,RAM BCLR 1,R0 BCLR [A0] Set this bit Bits can be addressed within a byte, or directly from an offset in a 64Kbit (8KB) range. BSET 2,RAM+5 Or BSET dest BCLR dest

15. © 2008, Renesas Technology America, Inc., All Rights Reserved 15 String Move Forward Instruction SMOVF.size Repeat M(A1)  M(2^16 X R1H + A0) A0  A0 +2 (increments by 1 if size = B) A1  A1 +2 ( increments by 1 is size = B) R3  R3 - 1 Until R3 = 0 SIZE = W OR B Note: The M16C architecture also has a SMOVB instruction that decrements the address pointers. 1. If A0 overflows, R1H is incremented. 2. If R3 is set to 0, this instruction is ignored. 3. Only the source can be Far data. 4. If an interrupt occurs, the interrupt will be acknowledged after one data transfer.

17. © 2008, Renesas Technology America, Inc., All Rights Reserved 17 Push Multiple Instructions PUSHM src  This instruction saves the registers selected by src to the stack area.  Registers are saved to the stack area in the following order: FB SB A1 A0 R3 R2 R1 R0 PUSHM R2,R1,R0 PUSHM FB,SB Saved sequentially beginning with FB b0 b7 In this example, the data in R0, R1, and R2 are being saved to the stack and the actual operand value would be 7. In this example, the operand value would be “C0” hex. The PUSHM and POPM instructions are also useful when register information must be stored before an operation; e.g., as part of a subroutine call.

18. © 2008, Renesas Technology America, Inc., All Rights Reserved 18 Pop Multiple Instructions POPM dest  This instruction restores the registers selected by dest from the stack area.  The registers are restored in the following order: FB SB A1 A0 R3 R2 R1 R0 POPM R2,R1,R0 POPM FB,SB Restored sequentially beginning with R0 b0b7 In this example, R0, R1, and R2 are being restored from the stack and the operand would be 7. In this example, the operand would be C0 hex.

19. © 2008, Renesas Technology America, Inc., All Rights Reserved Optimized C Language Instructions main( ) { int i, j ; i = j = 0 ; i = j + 5 ; } ………………. 2 int. areas (total of 4 bytes) Return from function. ENTER #4 EXITD Creates Stack Frame [3-byte instruction] [2-byte instruction] Return address Return address FB SP Return address FB Return address FB j i SP Return address FB SP Remove Auto Area Return (Restore PC) Put SP to FB Move SP by 4 bytes Save FB Removes Stack Frame Return address FB j i SP Return address SP Restore FB SP PC saved by JSR ENTER and EXITD

20. © 2008, Renesas Technology America, Inc., All Rights Reserved 20 Sum-of-Products Instruction Multiplicand address : A0 Multiplier address : A1 Sum-of product calculation number : R3 Sum-of products register (result of operation) : R2R0 ( if.W is specified); R0 ( if.B is specified)  If an overflow occurs during operation, the O flag is set to terminate the operation.  If an interrupt request is received during instruction execution, the interrupt is acknowledged after the sum-of products addition has been completed. RMPA.size

22. © 2008, Renesas Technology America, Inc., All Rights Reserved 22 Course Summary Instruction set and addressing modes Execution instruction times Near and Far memory Powerful instructions of the M16C core  Multiply  Divide  Bit Manipulation  ENTER/EXITD  PUSHM/POPM  RMPA  SMOVF