1. COMP541 Sequential Logic – 3: Verilog Descriptions
Montek Singh
Mar 7, 2016

2. Today’s Topics Verilog styles for FSM State machine styles
Don’t forget to check synthesis output and console msgs.
State machine styles
Moore vs. Mealy

3. Verilog coding styles for FSMs

4. Verilog coding styles
First: More on Verilog procedural/behavioral statements
if-then-else
case statement
Then: How to specify an FSM
Using two always blocks
Using a single always block??
Using three always blocks

5. Verilog procedural statements
All variables/signals assigned in an always statement must be declared as logic
Why?
Because always allows intermittent updates to a signal
So, the signal could turn out to be combinational or sequential…
… depending on the actual description

6. Verilog procedural statements
These statements are often convenient:
if / else
case, casez
more convenient than “? : ” conditional expressions
especially when deeply nested
But: these must be used only inside always blocks
some genius decided that!
Result:
designers often want to use if-else/case for describing combinational logic for convenience/readability
… instead of being limited to just “? : ” expressions
so SystemVerilog introduced a new construct: always_comb
the compiler will try to check to see that the description is indeed a combinational function

7. Example: Comb. Logic using case
module decto7seg(input wire [3:0] data,
output logic [7:0] segments); // no flipflops actually
always_comb // used -> combinational
case (data)
0: segments <= 8’b ;
1: segments <= 8’b ;
2: segments <= 8’b ;
3: segments <= 8’b ;
4: segments <= 8’b ;
5: segments <= 8’b ;
6: segments <= 8’b ;
7: segments <= 8’b ;
8: segments <= 8’b ;
9: segments <= 8’b ;
default: segments <= 8’b ; // required!!
endcase
endmodule
Note the “comb”:
it means that the compiler will check to make sure that the output is combinational.

8. Example: Comb. Logic using case
module decto7seg(input wire [3:0] data,
output logic [7:0] segments); // no flipflops actually
always_comb // used -> combinational
case (data)
0: segments <= 8’b ;
1: segments <= 8’b ;
2: segments <= 8’b ;
3: segments <= 8’b ;
4: segments <= 8’b ;
5: segments <= 8’b ;
6: segments <= 8’b ;
7: segments <= 8’b ;
8: segments <= 8’b ;
9: segments <= 8’b ;
default: segments <= 8’b ; // required!!
endcase
endmodule
Suppose we forget to include the default case. What have we described then?
An incomplete case statement would imply that segments should hold its value if no cases match!

9. Beware the unintended latch!
Very easy to unintentionally specify a latch/register in Verilog!
how does it arise?
you forgot to define output for some input combination
in order for a case statement to imply combinational logic, all possible input combinations must be described
one of the most common mistakes!
one of the biggest sources of headache!
you will do it a gazillion times
this is yet another result of the hangover of software programming
forgetting everything in hardware is parallel, and time is continuous

10. Beware the unintended latch!
Solution
good programming practice
use always_comb
remember to use a default statement with cases
every if must have a matching else
check synthesizer output / console messages
a good compiler will often issue a warning for an unintended latch

11. Beware the unintended latch!
Example: multiplexer
out is output of combinational block
no latch/register is intended in this circuit
recommended Verilog:
assign out = select? A : B;
But, an if statement (inside an always block) will incorrectly introduce a latch/register:
if (select) out <= A;
if (!select) out <= B;
storage element added to save old value if condition is false
to avoid creating storage, cover all cases in one statement:
else out <= B;
select A B
out

12. Combinational Logic using casez
casez allows case patterns to use don’t cares
module priority_casez(input wire [3:0] a,
output logic [3:0] y);
// y will be combinational
always_comb
casez(a)
4’b 1???: y <= 4’b 1000; // ? = don’t care
4’b 01??: y <= 4’b 0100;
4’b 001?: y <= 4’b 0010;
4’b 0001: y <= 4’b 0001;
default: y <= 4’b 0000;
endcase
endmodule

13. Blocking vs. Non-blocking Assignment
Blocking assignments:
Equal sign indicates blocking statements
occur in text order
B = A;
C = B;
Result: new contents of B are in C, so all have contents of A
Non-blocking assignments:
RHS of all <= lines within a begin-end block are evaluated in parallel, then assigned to LHS signals in parallel
B <= A;
C <= B;
Result: new B is the value of A, but new C is the old B!

14. Cheat Sheet for comb. vs seq. logic
Sequential logic:
Use clk)
Use nonblocking assignments (<=)
Do not make assignments to the same signal in more than one always_ff block!
e.g.:
clk)
q <= d; // nonblocking

15. Cheat Sheet for comb. vs seq. logic
Combinational logic:
Use continuous assignments (assign …) whenever readable
assign y = a & b; OR
Use always_comb
All variables must be assigned in every situation!
must have a default case in case statement
must have a closing else in an if statement
do not make assignments to the same signal in more than one always_comb or assign statement

16. Revisit the sequence recognizer
(from last lecture)
Let us describe this as a Mealy FSM in SystemVerilog

17. Let’s encode states using enum
State encoding: convert symbolic state names to binary values
e.g., states = A, B, C, D
A=00, B=01, C=10, D=11
SystemVerilog provides enum construct
similar to C/Java
set of predefined constants
aids readability (and type/range checking in Java)
enum { A = 2’b 00, B = 2’b 01, C = 2’b 10, D = 2’b 11 } state, next_state;
also possible to leave encoding to compiler
enum { A, B, C, D } state, next_state;

18. FSM in SystemVerilog Step 1: State encoding module seq_rec (
input wire CLK, RESET, X,
output logic Z);
enum { A, B, C, D } state, next_state;
// Leaving encoding to compiler

19. Step 2: Next State logic Next State logic should be combinational
always_comb
case (state)
A: if (X == 1) next_state <= B;
else next_state <= A;
B: if(X) next_state <= C; else next_state <= A;
C: if(X) next_state <= C; else next_state <= D;
D: if(X) next_state <= B; else next_state <= A;
default: next_state <= A;
endcase
The last 3 cases do same thing.
Just sparse syntax.

20. Step 3: State Register Register with reset synchronous reset (Lab 5)
reset occurs only at clock transition
CLK)
if (RESET == 1) state <= A;
else state <= next_state;
prefer synchronous reset
asynchronous reset
reset occurs whenever RESET goes high
CLK or posedge RESET)
use asynchronous reset only if you really need it!

21. Step 4: Output logic Output logic must be combinational always_comb
case(state)
A: Z <= 0;
B: Z <= 0;
C: Z <= 0;
D: Z <= X ? 1 : 0; // OR: Z <= X
default: Z <= 0;
endcase

22. Most common template for Mealy FSM
Use 3 always blocks
2 combinational logic
one for next state
one for outputs
1 state register
 easy to see everything clearly!

23. Final FSM in SystemVerilog
module seq_rec (
input wire CLK, RESET, X,
output logic Z);
enum { A, B, C, D } state, next_state;
always_comb // Process 1
case (state)
A: if (X == 1) next_state <= B;
else next_state <= A;
B: if(X) next_state <= C; else next_state <= A;
C: if(X) next_state <= C; else next_state <= D;
D: if(X) next_state <= B; else next_state <= A;
default: next_state <= A;
endcase
CLK) // Process 2
if (RESET == 1) state <= A;
else state <= next_state;
always_comb // Process 3
case(state)
A: Z <= 0;
B: Z <= 0;
C: Z <= 0;
D: Z <= X ? 1 : 0;
default: Z <= 0;
endcase

24. Comment on Code Could shorten it somewhat Template helps synthesizer
Don’t need three always_ clauses
Although it’s clearer to have combinational code be separate
Don’t need next_state, for example
Can just combine next_state logic with state update
Template helps synthesizer
Check to see whether your state machines were recognized by compiler (see output log)

25. Verilog: specifying FSM using 2 blocks
Let us divide FSM into two modules
one stores and update state
another produces outputs

26. FSM using two always blocks
module seq_rec (
input wire CLK, RESET, X,
output logic Z);
enum { A, B, C, D } state, next_state;
CLK) // Process 1
begin
if (RESET == 1) state <= A;
else case (state)
A: if (X == 1) state <= B;
else state <= A;
B: if(X) state <= C; else state <= A;
C: if(X) state <= C; else state <= D;
D: if(X) state <= B; else state <= A;
default: state <= A;
endcase // default not required
// for sequential logic!
end
always_comb // Process 2
case(state)
A: Z <= 0;
B: Z <= 0;
C: Z <= 0;
D: Z <= X ? 1 : 0;
default: Z <= 0;
endcase

27. Incorrect: Putting all in one always
Using one always block
generally incorrect! (But may work for Moore FSMs)
ends up with unintended registers for outputs!
AVOID!
CLK) // a single process for entire FSM
case (state)
A: if(X) begin state <= B; Z <= 0; end;
B: if(…) begin state <= C; Z <= 1; end;
C: if(…) begin state <= …; Z <= …; end;
D: if(…) begin state <= …; Z <= …; end;
endcase

28. My Preference The one with 3 always blocks Follow my template
Easy to visualize the state transitions
For really simple state machines:
2 always blocks is okay too
Never put everything into 1 always block!
Follow my template
lab6_fsm_template.sv (posted on the website)
FSM’s inputs and outputs are described as multibit signals
input wire [M-1:0] INPUTS
output logic [N-1:0] OUTPUTS
But: usually better to separate them into individual signals
input wire x, y, z
output logic o1, o2

29. Moore vs. Mealy FSMs?
So, is there a practical difference?

30. Moore vs. Mealy Recognizer
Mealy FSM: arcs indicate input/output

31. Moore and Mealy Timing Diagram

32. Moore vs. Mealy FSM Schematic

33. Next
Timing of Sequential Circuits