1. Reconfigurable Computing1 Reconfigurable Computing Part II

2. Reconfigurable Computing2 Roadmap of Presentation Static and Dynamic Configurable Systems Piperench: A Reconfigurable Architecture and Compiler

3. Reconfigurable Computing3 Static & Dynamic Reconfiguration Static: Configuration string is loaded once and does not change until the end of the task Dynamic: Configuration can change at any point

4. Reconfigurable Computing4 Objectives of Static Configuration 1. Improvement of Performance 2. Optimizing the utilization of resources (gates & power consumption....)

5. Reconfigurable Computing5 An Application of Static Configuration: SPYDER A reconfigurable co-processor adaptable to given application in a transparent way The application is written with a high level language, compiler generates the best description for the hardware

6. Reconfigurable Computing6 System Description of SPYDER Reconfiguration takes place in processing unit composed of 3 FPGAs connected to two register banks Each FPGA has independent access to registers for parallel processing FPGA size & # registers are limitations for configuration!

7. Reconfigurable Computing7 User Configuration First aim was transparent HW configuration The user just determines the operators in a high level language Compiler then generates the corresponding code and does operations based on maximal parallelism.

8. Reconfigurable Computing8 SPYDER Architecture

9. Reconfigurable Computing9 Performance Performance of SPYDER surpasses that of classical architectures. SPYDER @8MHz computes the future states of 115M cells, while SPARC @85MHz can do 6.5M states.(skeletonization, edge detection)

10. Reconfigurable Computing10 Another Static Configuration Application: RENCO A reconfigurable network computer for improved performance of the system RENCO adds the power of reconfiguration to the network computer. User can download not only his/her application but also the processor configuration

11. Reconfigurable Computing11 Hardware Composed of two parts: 1.A conventional network computer with a processor: Motorola MC68EN360 RENCO’s µ-processor has high communication capabilities, integrated memory controller, and many SW tools are available. 2.A reconfigurable part: A cluster of FPGAs connected to their own memories and processor buses

12. Reconfigurable Computing12 Hardware Reconfigrable part contains 4 Altera Flex FPGAs. Each has up to 1M logic gates Processor bus is connected to 4 FPGAs so that they can act as co-processors and each FPGA memories can be accessed by the processor. 14 layer PCB!

13. Reconfigurable Computing13 RENCO Block Diagram

14. Reconfigurable Computing14 Software Network computer requires a good OS for networking For reconfigurable part many SW tools are availale(synthesizer, monitor for resource access & configuration loading, debugger etc) Java(Kaffe) is used for source code. HW libraries are built accordingly So like other reconfigurable systems SW is much harder than HW!

15. Reconfigurable Computing15 Performance Since HW libraries are currently unavailable cannot make proper evaluation for performance However the idea of downloadable HW architecture is amazing. Also this idea can be used as prototype for complex logic design

16. Reconfigurable Computing16 Objective of DYNAMIC Configuration To handle changing and/or incomplete specifications

17. Reconfigurable Computing17 An Application of Dynamic Configuration: FIREFLY Based on the idea of applying the biological principle of natural evolution to artificial systems A genetic algorithm is iterative procedure that starts with a random initial population

18. Reconfigurable Computing18 General Description Aim is to reach the “best individuals” by evolutionary steps in which the individuals are evaluated according to some predefined quality criterion In order to create next generation, individuals are subjected to genetic operators(cross-over, mutation, etc...) This iteration with these operations results in the best generation Firefly machine implements this algorithm in a reconfigurable manner

19. Reconfigurable Computing19 Structure Firefly is based on cellular automata model consisting of an array of cells whose states are updated in every evolutionary step. A rule table, concerning the neighbour’s state, exists for the determination of the next state After some steps iteration leads the cells to oscillate between all 0’s and all 1’s. Firefly inherits its name from this phenomenon

20. Reconfigurable Computing20 Hardware Firefly has 56 cells consisting of FPGA’s as the evolution platform. Firefly is a machine in which all the system evolution is carried out online, that is in hardware! Evolution rules and state of a cell are stored in D-flipflops.

21. Reconfigurable Computing21 FireFly Board

22. Reconfigurable Computing22 Performance and Future All operation are carried our in HW with no external reference High performance workstation execute 60 configurations while Firefly can execute 13000 configurations per second Evolving machines(like Firefly) operating in autonomous manner can be used in the field of autonomous robots and of controllers for noisy and changing environments.

23. Reconfigurable Computing23 Another Application of Dynamic Reconfiguration: BIOWATCH Objective is to development of VLSICs capable of self repair and self replication Biowatch is an artificial organism deigned to count seconds & minutes thus a modulo-3600 counter. Multicellular organism each cell realizing a unique function described by the gene of the cell.

24. Reconfigurable Computing24 Functioning Dynamic reconfiguration of the executing task occurs during the self- repair process The cells interprets the the genome(whole set of genes) The cell executes the operations According to the relevant part of the genomes(genes) which configures it

25. Reconfigurable Computing25 Hardware Coarse grained FPGAs are used. Each cell holds a 4-bit state register. 4 four-bit buses enter the cells from the neigbour cells. 4 output buses also go to neighbours Binary decision machine of the cell executes µ-programs(genomes) written using a set of 6 instructions Each cell is implemented in a Actel 1020 FPGA circuit

26. Reconfigurable Computing26 Self Repair Self repair of artificial organism allows partial reconstruction of the original device in case of a minor fault Faulty Cell is by-passed and all or a part original cellular array is shifted to the right New Coordinates lead to dynamic configuration of the executing task of cell

27. Reconfigurable Computing27 Self Repair

28. Reconfigurable Computing28 Self Replication Self repair of an artificial organism allows for the complete reconstruction of the original device in case of a major fault

29. Reconfigurable Computing29 PIPERENCH: A Reconfigurable Architecture

30. Reconfigurable Computing30 Pipelined Reconfiguration Piperench, a new reconfigurable fabric, combines the flexibility of conventional procesors with the efficiency of custom HW to achieve extreme performance speed-up Piperench is a reconfigurable fabric consisting of an interconnected network of configurable logic and storage elements. Pipelined reconfiguration implements a large logical configuration on a small piece of HW through rapid reconfiguration of that HW

31. Reconfigurable Computing31 General Procedure Pipelined reconfiguration involves virtualizing pipelined computations by breaking a single static configuration into pieces Each piece of configuration corresponds to pipeline stages in the application Physically 3 but functionally 5 stages!

32. Reconfigurable Computing32 Virtualization Process Stage1 configured in cycle 1, and executes for two cycles. There is no physical pipe stage 4, therefore in cycle 4 the fourth virtual pipe stage is configured in physical stage 1

33. Reconfigurable Computing33 Virtualization Process

34. Reconfigurable Computing34 Virtualization Process Reconfiguration does not decrease performance since some stages are configured while others are executed Configuration takes 1 cycle in successfull applications since wide on- chip configuration buffer and a small controller are employed

35. Reconfigurable Computing35 Stripe(Pipeline Stage)

36. Reconfigurable Computing36 Stripe Architecture Piperench contains a set of physical pipeline stages called stripes Each PE contains ALU each of which contain LUTs

37. Reconfigurable Computing37 Benefits of Piperench Improved Compilation Time Improved Reconfiguration Time

38. Reconfigurable Computing38 References “Static and Dynamic Configurable Systems” “Piperench: A Reconigurable Architecture and Compiler” “Reconfigurable Conputer Architectures and Design Methods”