1. Power Supply for DEPFET in SuperBelle Pablo Vazquez IGFAE-USC Henryk Palka INP-KRA

2. Current layout (Belle) SVD power supplies (Kenwood) Racks on a platform behind the barrel Thick cables (60mΩ/11m) DOCK (x4): contains repeaters, regulators etc, Al box with water cooling, Fixed into 4 ‘compartments In the barrel face Thin cables (190mΩ/8m) No radiation ‘some radiation’ measured fast neutron dose: ~1.5mSv/2weeks @ L=1.5*10 34 @ L=2*10 35 : 15x  600 mSv/year ≈ 10 8 n/cm 2 /yr

3. New CDC design  more space for cabling in FW (+ something else?) sBelle 250mm 300mm 350mm 100mm More space, But IP region not fixed yet (will change!)

4. DOCKs 40 x 20 x12cm (LxWxH) Al boxes, water cooled, overcrowded now, at cooling limit Only 4 ‘compartments, on each side Probably more needed for the new strip det. + PXD !  Request to mechanics designers to forsee more space

5. Current voltage list available on the twiki DeviceDomainVoltageCurrentNet nameComment DEPFETsource7V???VSOURCE common clear gate7V???VCCG bulk17V???VBULK back plane-20V???VBP50µ thick sensor! guard ring???V???VGUARDreplaces VEDGE DCD2analog1.8V100mAVDDA analog0.35V-30mAAmpLow analog0.77V-60mAVcascAmpVSS / VCAVSS digital1.8V40mAVDDlvds / LVDS analog1.1V15mARefIn gnd0V50mADGND Switcher5digital3.3V???DVDD_S digital ret.0V???DGNDcommon digital ground Clear_off(min-max)V???CLEAR_OFF Clear_on(min-max)V???CLEAR_ON Gate_off(min-max)V???GATE_OFF Gate_on(min-max)V???GATE_ON DHPdigital_core1.0V???DVDD_CORE digital_IO1.8V - 2.5V???DVDD_IO digital ret.0V???DGNDcommon digital ground Still many missing Parameters!!! We need some basics http://aldebaran.hll.mpg.de/twiki/bin/view/DepfetInternal/PowerSupplyScheme

6. A tentative of a scheme Power unit (rack) Regulators, DCD card(s) (dock, water cooling) DHH goup main power lines - analog / digital - similar final voltage - balanced current - positive / negative (Vbackplane) - in example 3 main lines per half-module - depfet voltages (“high” voltages, low current) - analog - digital Functionalities: - Regulators, space for sensing lines on cable? - Need to tune voltages by software? => less robust than hardware settings - Need to switch on digitial part and then analog? Half-module ~11m~8m ~1m? x 22

7. PS power rating Inner layer superBelle module (7.1 x 0.8 cm 2, 50x50  m 2 pixel): Matrix: active pixel: 500  W x 640 0.3 W Switcher III* active row: 225 mW x 2 0.45 W active chip: 50 mW x 2 0.1 W idle chips: 10 mW x 10 0.1 W DCD1 (readout)* per channel: 5 mW x 20483.2 W ( * New ASIC versions) 4.15 W per module Estimate by H-G Moser (S-Belle Coll. Meeting March 2008): 44 modules x (4.15 + regulators + DHP + DHH + safety) > 500W  need to be updated and fixed... at some point

8. Slow controls A minimum finctionality: - voltage & current measurements and regulation - ramping - interlocks - temperature measurements, where? humidity? - radiation dose Probably as a part of the PS system  interface to be decided (JTAG?) Currently no Slow Control standard in Belle – each subdetector does it their own way SVD: V,I by built-in monitors of KENWOOD PS temperatures: by IOTECH data loggers interlocks separately (bad idea) Toru Tsuboyama: Samo Stanic was asked to think/design a new monitoring system whe should be in contact controlled by GPIB

9. Sumary - Work on power supply with slow control workpackage (1.7.2) has started - Place for power units and regulation boards identified - Space for cables and boards will need to be requested - Many paramenters (V/I) on the electronics are still unknown, I now ASICS are under development but some baseline scenario is needed - Need to define temperature, humidity? probes, interlocks, radiation? - Common grounding policy for the experiment unclear (does it exist?) - No common slow control for Belle, not foreseen for SuperBelle, if possible could be interesting join SVD effort

10. New CDC design