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Wujie Wen, Assistant Professor Department of ECE

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1 Wujie Wen, Assistant Professor Department of ECE
EEL 6167: VLSI Design Lecture 4: Review Wujie Wen, Assistant Professor Department of ECE EL3193. Slides adapted from Harris’ slides from Harvey Mudd. Copyright 2005 Addison-Wesley and Rabaey’s Digital Integrated Circuits, Copyright 2002, J. Rabaey et al.

2 Outline Review of Last lecture Homework 2 Quiz 1 Homework 1
5: DC and Transient Response

3 Pass Transistors We have assumed source is grounded
What if source > 0? e.g. pass transistor passing VDD Vg = VDD If Vs > VDD-Vt, Vgs < Vt Hence transistor would turn itself off nMOS pass transistors pull no higher than VDD-Vtn Called a degraded “1” Approach degraded value slowly (low Ids) pMOS pass transistors pull no lower than Vtp Transmission gates are needed to pass both 0 and 1 5: DC and Transient Response

4 Pass Transistor Ckts 5: DC and Transient Response

5 DC Response DC Response: Vout vs. Vin for a gate Ex: Inverter
When Vin = 0 -> Vout = VDD When Vin = VDD -> Vout = 0 In between, Vout depends on transistor size and current By KCL, must settle such that Idsn = |Idsp| We could solve equations But graphical solution gives more insight 5: DC and Transient Response

6 Transistor Operation Current depends on region of transistor behavior
For what Vin and Vout are nMOS and pMOS in Cutoff? Linear? Saturation? 5: DC and Transient Response

7 nMOS Operation Cutoff Linear Saturated Vgsn < Vtn Vin < Vtn
Vdsn < Vgsn – Vtn Vout < Vin - Vtn Vdsn > Vgsn – Vtn Vout > Vin - Vtn Vgsn = Vin Vdsn = Vout 5: DC and Transient Response

8 pMOS Operation Cutoff Linear Saturated Vgsp > Vtp
Vin > VDD + Vtp Vgsp < Vtp Vin < VDD + Vtp Vdsp > Vgsp – Vtp Vout > Vin - Vtp Vdsp < Vgsp – Vtp Vout < Vin - Vtp Vgsp = Vin - VDD Vdsp = Vout - VDD Vtp < 0 5: DC and Transient Response

9 I-V Characteristics Make pMOS is wider than nMOS such that bn = bp
5: DC and Transient Response

10 Current vs. Vout, Vin 5: DC and Transient Response

11 Load Line Analysis For a given Vin: Plot Idsn, Idsp vs. Vout
Vout must be where |currents| are equal in 5: DC and Transient Response

12 Load Line Analysis Vin = 0 Vin = 0 0.2VDD VDD 0.8VDD 0.6VDD 0.4VDD
5: DC and Transient Response

13 DC Transfer Curve Transcribe points onto Vin vs. Vout plot
5: DC and Transient Response

14 Operating Regions Revisit transistor operating regions Region nMOS
pMOS A Cutoff Linear B Saturation C D E 5: DC and Transient Response

15 Beta Ratio If bp / bn  1, switching point will move from VDD/2
Called skewed gate Other gates: collapse into equivalent inverter 5: DC and Transient Response

16 Noise Margins How much noise can a gate input see before it does not recognize the input? 5: DC and Transient Response

17 Logic Levels To maximize noise margins, select logic levels at
unity gain point of DC transfer characteristic 5: DC and Transient Response

18 Transient Response DC analysis tells us Vout if Vin is constant
Transient analysis tells us Vout(t) if Vin(t) changes Requires solving differential equations Input is usually considered to be a step or ramp From 0 to VDD or vice versa 5: DC and Transient Response

19 Inverter Step Response
Ex: find step response of inverter driving load cap 5: DC and Transient Response

20 Delay Definitions tpdr: rising propagation delay
From input to rising output crossing VDD/2 tpdf: falling propagation delay From input to falling output crossing VDD/2 tpd: average propagation delay tpd = (tpdr + tpdf)/2 tr: rise time From output crossing 0.2 VDD to 0.8 VDD tf: fall time From output crossing 0.8 VDD to 0.2 VDD 5: DC and Transient Response

21 Delay Definitions tcdr: rising contamination delay
From input to rising output crossing VDD/2 tcdf: falling contamination delay From input to falling output crossing VDD/2 tcd: average contamination delay tpd = (tcdr + tcdf)/2 5: DC and Transient Response

22 Simulated Inverter Delay
Solving differential equations by hand is too hard SPICE simulator solves the equations numerically Uses more accurate I-V models too! But simulations take time to write, may hide insight 5: DC and Transient Response

23 Delay Estimation We would like to be able to easily estimate delay
Not as accurate as simulation But easier to ask “What if?” The step response usually looks like a 1st order RC response with a decaying exponential. Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R So that tpd = RC Characterize transistors by finding their effective R Depends on average current as gate switches 5: DC and Transient Response

24 Effective Resistance Shockley models have limited value
Not accurate enough for modern transistors Too complicated for much hand analysis Simplification: treat transistor as resistor Replace Ids(Vds, Vgs) with effective resistance R Ids = Vds/R R averaged across switching of digital gate Too inaccurate to predict current at any given time But good enough to predict RC delay 5: DC and Transient Response

25 RC Delay Model Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C Capacitance proportional to width Resistance inversely proportional to width 5: DC and Transient Response

26 RC Values Capacitance C = Cg = Cs = Cd = 2 fF/mm of gate width in 0.6 mm Gradually decline to 1 fF/mm in 65 nm Resistance R  10 KW•mm in 0.6 mm process Improves with shorter channel lengths 1.25 KW•mm in 65 nm process Unit transistors May refer to minimum contacted device (4/2 l) Or maybe 1 mm wide device Doesn’t matter as long as you are consistent 5: DC and Transient Response

27 Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter d = 6RC 5: DC and Transient Response

28 Delay Model Comparison
5: DC and Transient Response

29 Example: 3-input NAND Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). 2 2 2 3 3 3 5: DC and Transient Response

30 3-input NAND Caps Annotate the 3-input NAND gate with gate and diffusion capacitance. 5: DC and Transient Response

31 Elmore Delay ON transistors look like resistors
Pullup or pulldown network modeled as RC ladder Elmore delay of RC ladder 5: DC and Transient Response

32 Example: 3-input NAND Estimate worst-case rising and falling delay of 3-input NAND driving h identical gates. 5: DC and Transient Response

33 Delay Components Delay has two parts Parasitic delay 9 or 12 RC
Independent of load Effort delay 5h RC Proportional to load capacitance 5: DC and Transient Response

34 Contamination Delay Best-case (contamination) delay can be substantially less than propagation delay. Ex: If all three inputs fall simultaneously 5: DC and Transient Response

35 Diffusion Capacitance
We assumed contacted diffusion on every s / d. Good layout minimizes diffusion area Ex: NAND3 layout shares one diffusion contact Reduces output capacitance by 2C Merged uncontacted diffusion might help too 5: DC and Transient Response

36 Layout Comparison Which layout is better? 5: DC and Transient Response

37 Reading and Homework Chapter 2 (2.5-2.5.4) Chapter 4 (4.2-4.3.6)
HW (P91) HW (P91) Know the research trend and industry trend about the EDA society, the VLSI Design 0: Introduction

38 Homework HW3----Assume you a full adder with three inputs A, B, Cin (count in) and two outputs S and Cout 1 The true table for the full adder The Boolean function of S and Cout Draw the complementary CMOS transistor schematic for S and Cout. Know the research trend and industry trend about the EDA society, the VLSI Design 0: Introduction

39 Homework HW4- Sketch a transistor-level schematic for a compound CMOS logic gate for each of following functions (size the transistor widths to achieve effective rise and fall resistances equal to a unit inverter (R).) Unit nMOS has resistance R, capacitance C Unit pMOS has resistance 2R, capacitance C 1: Circuits & Layout

40 Homework HW5- Simple CMOS Circuits. Fill in the table below, indicating for each input combination which transistors are “ON” or “OFF.” If “Hi” is a logic 1 and “Low” is a logic 0, show the logic output. What is the logic function? 1: Circuits & Layout

41 Homework Reading Chapter 1 Introduction Section 1.3/1.4/1.5/1.6
Homework 1 (No , hardcopy) 1 Sketch a transistor-level schematics for 1: Circuits & Layout

42 Homework Reading -chapter 1 introduction Section 1.3/1.4/1.5/1.6
Homework (No , hard-copy only, due Nov. 7th) HW1: Sketch a transistor-level schematics for a CMOS 5 input NAND gate 1: Circuits & Layout

43 Homework HW2- Sketch a transistor-level schematic for a compound CMOS logic gate for each of following functions 1: Circuits & Layout

44 Homework HW3- Draw a transistor diagram for a tri-state 2 input NAND, with 3 inputs labeled A, B, EN. You can assume you have not(EN) 1: Circuits & Layout

45 Homework HW4- Assume you have a 2 to 1 multiplexer,
try to design OR/ AND / XOR gate only from it (not gate is not available) Draw the transistor diagram of XOR (assume you have not gate ready for simplicity) 1: Circuits & Layout

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