1. FET
FET’s (Field – Effect Transistors) are much like BJT’s (Bipolar Junction Transistors).
Similarities:
• Amplifiers
• Switching devices
• Impedance matching circuits
Differences:
• FET’s are voltage controlled devices whereas BJT’s are current controlled devices.
• FET’s also have a higher input impedance, but BJT’s have higher gains.
• FET’s are less sensitive to temperature variations and because of there construction they are more easily integrated on IC’s.
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2. FET Types • JFET ~ Junction Field-Effect Transistor
• MOSFET ~ Metal-Oxide Field-Effect Transistor
- D-MOSFET ~ Depletion MOSFET
- E-MOSFET ~ Enhancement MOSFET

3. Categories FET METAL-OXIDE semiconductor JUNCTION Depletion Depletion
Enhancement
P channel
N channel
P channel
N channel
P channel
N channel

4. Junction Field Effect Transistor
(JFET)

5. THE JUNCTION FIELD-EFFECT TRANSISTOR (JFET)
The JFET is a type of FET that operates with a reverse-biased junction to control current in the channel

6. JFET Symbols

7. JFET Basic Operation - The JFET is always operated with++
JFET Basic Operation
IDS
VGS <= 0 - +
The JFET is always operated with
Drain-to-Source
channel of current (เส้นทางการเดินของกระแส)
n-channel or p-channel
Gate-to-Source pn junction reverse-biased
a door to control amount of current flow between Drain-Source
VGS (CUT_OFF) <= VGS <= 0

8. How VGS control IDS? การควบคุมกระแส IDS ทำได้โดย |VGS |= 0
การปรับการขยายตัวของ depletion region ระหว่าง Gate กับ channel
|VGS |= 0
ให้ค่ากระแส IDS สูงที่สุด
ประตูปิดช้า กระแสไหลผ่านได้มาก
|VGS | < 0
ให้ค่ากระแส IDS น้อยลง
เร่งให้ประตูปิดเร็วขึ้น กระแสไหลได้น้อยลง

9. Relationship between VGS and IDS
IDS(1) = k1
VGS(2) = -a2
IDS(2) = k2
|VGS |: a1 < a2 < a3
IDS: k1 > k2 > k3
VGS(3) = -a3
IDS(3) = k3

10. VGS controls ID. JFET must be operated between VGS =0 and VGS(off)
VGS (off) = VGS (MAX) -> IDS = 0

11. JFET Construction
There are two types of JFET’s: n-channel and p-channel.
The n-channel is more widely used.
There are three terminals: Drain (D) and Source (S) are connected to n-channel
Gate (G) is connected to the p-type material
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12. FIGURE 5-5 Varying reverse-bias potentials across the p-n junction of an n-channel JFET.
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13. A. VGS = 0, VDS increasing to some positive value
Three things happen when VGS = 0 and VDS is increased from 0 to a more positive voltage:
• the depletion region between p-gate and n-channel increases as electrons from
n-channel combine with holes from p-gate.
• increasing the depletion region, decreases the size of the n-channel which increases the resistance of the n-channel. • But even though the n-channel resistance is increasing, the current (ID) from Source to Drain through the n-channel is increasing. This is because VDS is increasing.
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14. Pinch-off
If VGS = 0 and VDS is further increased to a more positive voltage, then the depletion zone gets so large that it pinches off the n-channel. This suggests that the current in the n-channel (ID) would drop to 0A, but it does just the opposite: as VDS increases, so does ID.
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15. JFET CHARACTERISTICS
IDSS is maximum drain current occurring for VGS =0 V,
and the value of VDS which ID becomes constant is the
pinch-off voltage

16. Comparison of Pinch-Off and Cutoff
Vp is the value of VDS
which the drain current becomes constant
and is always measured at VGS =0 V
VGS(off) and Vp are always equal in magnitude but opposite in sign

17. Transfer Curve
From this graph it is easy to determine the value of ID for a given value of VGS.
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18. The transfer characteristic of input-to-output is not as straight forward in a JFET as it was in a BJT.
In a BJT,  indicated the relationship between IB (input) and IC (output).
In a JFET, the relationship of VGS (input) and ID (output) is a little more complicated:
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19. DC Bias for JFET 2 types of DC bias for JFET Fixed bias Self bias
- 2 sources
Self bias
- Single source ( 1 source)

20. DC bias for JFET Fixed bias (2 DC sources)

21. Load Line for JFET DC bias Fixed bias (ID, VDS)RD RG
VDD
IDS
Load Line: VDS vs IDS

22. Load Line for JFET DC bias Fixed bias (ID, VGS)
VGSQ=-2V, IDQ=5.625mA, VDS = 4.75V

23. DC bias for JFET Self bias (Single Source)RD
VDD RG RS
IDS
VG = 0
Load Line: VDS vs IDS

24. DC bias for JFET Self bias (Single Source)

25. Example for JFET DC bias Self bias (Single Source)
VGSQ=-2.6V, IDQ=2.6mA

26. DC bias for JFET Voltage Divider Bias (Single Source)

27. Load Line for JFET DC bias Voltage Divider bias (ID, VDS)

28. Example for JFET DC bias Voltage Divider bias (Single Source)

29. P-channel JFET
p-Channel JFET acts the same as the n-channel JFET, except the polarities and currents are reversed.
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30. P-Channel JFET Characteristics
As VGS increases more positively:
• the depletion zone increases
• ID decreases (ID < IDSS)
• eventually ID = 0A
Also note that at high levels of VDS the JFET reaches a breakdown situation. ID increases uncontrollably if VDS > VDSmax.
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31. Specification Sheet (JFETs)
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32. MOSFETs
MOSFETs have characteristics similar to JFETs and additional characteristics that make then very useful.
- Low power consumption
- No gate current: SiO2 at Gate
There are 2 types:
• Depletion-Type MOSFET
• Enhancement-Type MOSFET
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33. Depletion MOSFET
(D-MOSFET)

34. THE METAL-OXIDE SEMICONDUCTOR FET(MOSFET)
Depletion MOSFET (D-MOSFET)
D-MOSFET can be operated either the depletion mode or the enhancement mode

35. D-MOSFET Symbols

36. Main Function of Depletion MOSFET
Control Current flow from Drain-to-Source

37. Two main control mode
Depletion mode
Enhancement mode

38. Depletion Mode N-channel Vgs -> negative
Electrons from D-to-S channel
Push to P-type substrate
The more the negative value of Vgs
The less amount of current flow from D-to-S

39. Enhancement mode N-channel Vgs -> positive
Electron from p-substrate
Pulled into D-to-S channel
Increase amount of electrions in the channel

40. Basic Operation (n-channel D-MOSFET)
A Depletion MOSFET can operate in two modes: Depletion or Enhancement mode.
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41. p-Channel Depletion-Type MOSFET
The p-channel Depletion-type MOSFET is similar to the n-channel except that the voltage polarities and current directions are reversed.
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42. Specification Sheet
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43. คุณลักษณะของ D-MOSFET
Channel การไหลของกระแสแคบกว่า JFET มาก
การเปิดปิดประตู (Gate) เพื่อควบคุมปริมาณกระแสให้ไหลตามต้องการได้เร็วกว่า JFET
Switching speed
On (กระแสไหล) -> Off (กระแสไม่ไหล) หรือ ในทางกลับกัน
เร็วกว่า JFET
เหมาะกับวงจร Digital ได้ดีกว่า JFET

44. Example for n-channel D-MOSFET DC bias Voltage Divider bias (Single Source)

45. Enhancement MOSFET
(E-MOSFET)

46. Enhancement MOSFET(E-MOSFET)

47. N-MOS

48. E-MOSFET symbol D S B G D S B G
N-channel
P-channel

49. คุณลักษณะของ E-MOSFET
ไม่มี channel ที่แท้จริง (no physical channel)
ใช้ virtual channel ที่สร้างขึ้นจาก
ใช้ VGS ควบคุม การมีหรือไม่มี virtual channel
การดึงดูด carrier ชนิดเดียวกับ channel มาเชื่อมช่องทางเดินกระแส เพื่อให้กระแส IDS เป็นตามต้องการ
Switching speed
ความเร็วในการให้กระแสไหล หรือ หยุดไหล เร็วมากกว่า
JFET และ D-MOSFET
หยุดป้อน VGS virtual channel หายไปเกือบจะทันที
นิยมใช้ใน Combinational Logic, CPU, Memory โดยเฉพาะ
CMOS ซึ่งเป็น E-MOSFET ชนิดหนึ่ง

50. How to induce the Channel D-to-S

51. source-drain current below saturation
Semiconductor Devices, 2/E by S. M. Sze, Copyright © 2002 John Wiley & Sons. Inc. All rights reserved.

52. source-drain current for pinch-off
Semiconductor Devices, 2/E by S. M. Sze, Copyright © 2002 John Wiley & Sons. Inc. All rights reserved.

53. source-drain current in saturation
Semiconductor Devices, 2/E by S. M. Sze, Copyright © 2002 John Wiley & Sons. Inc. All rights reserved.

54. Transfer Curve To determine ID given VGS: [Formula 5.13]
where VT = threshold voltage or voltage at which the MOSFET turns on.
k = constant found in the specification sheet
k can also be determined by using values at a specific point and the formula:
[Formula 5.14]
VDSsat can also be calculated:
[Formula 5.12]
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55. Load Line for n-channel E-MOSFET DC bias Voltage Divider bias (Single Source)
VDD = 40V, R1=22MOhm, R2=18MOhm, RD=3kOhm, Rs=0.82kOhm
E-MOSFET (2N4351): VGS(Th)=VT=5V, ID(on)=3mA, VGS(on)=10V
VGSQ=12.5V, IDQ=6.7mA

56. Load Line for n-channel E-MOSFET DC bias Feedback bias (Single Source)

57. Example for n-channel E-MOSFET DC bias Feedback bias (Single Source)

58. Specification Sheet
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59. VMOS VMOS – Vertical MOSFET increases the surface area of the device.
Advantage:
• This allows the device to handle higher currents by providing it more surface area to dissipate the heat.
• VMOSs also have faster switching times.
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60. CMOS
CMOS – Complementary MOSFET p-channel and n-channel MOSFET on the same
substrate.
Advantage:
• Useful in logic circuit designs
• Higher input impedance
• Faster switching speeds
• Lower operating power levels
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61. CMOS
N-MOS
P-MOS

62. From device to system Figure 1.5 SYSTEM MODULE + GATE CIRCUIT DEVICE Gn+ n+
Figure 1.5

63. Application of CMOS
Microprocessor

64. Transistor Counts 1 Billion Transistors K 1,000,000 100,000 10,000
Pentium® III
10,000
Pentium® II
Pentium® Pro
1,000
Pentium®
i486
i386
100
80286 10
8086
Source: Intel 1
1975
1980
1985
1990
1995
2000
2005
2010
Projected
Figure 1.1
Courtesy, Intel

65. Application of CMOS 1970: Fairchild introduces 256-bit Static RAMs
1970: Intel starts selling1K-bit Dynamic RAMs
Intel K-bit DRAM
Fairchild bit SRAM

66. Memory trends
Figure 1.2