1. Interrupt Handling Marcus Völp Universität Karlsruhe

2. Interrupts Sources Devices Other CPU Internal Goal: avoid polling with asynchronous signal Disk IO-Register 32 bit CPU RAM 1x polling = 1200 Cycles CPU overhead at 5 MB / s data transfer

3. Interrupts Sources Devices Other CPU Internal Goal: avoid polling with asynchronous signal Disk IO-Register 32 bit CPU RAM 1x polling = 1200 Cycles CPU overhead at 5 MB / s data transfer 104,9 %

4. Interrupts Sources Devices Other CPU Internal Goal: avoid polling with asynchronous signal Disk CPU RAM Interrupt signals end of DMA DMA

5. Exception / Interrupt Exception Fault (page fault) exception that can be corrected faulting instruction is restarted Trap(int X, sysenter) voluntary kernel entry restart after trapping instruction Abort(hw errors, illegal values in system table) exception that does not allow restart imprecise location SW-Interrupt == Trap (int X) HW-Interrupt asynchronous to instruction flow

6. Interrupt Descriptor Table HW-Interrupt Interrupt Controller int nr Exception / Soft int IDTR int 2 Gate int 3 Gate int 1 Gate int n Gate int 4 Gate int 5 Gate X int_X_handler: Handler Function: segment : offset Priviledge Level: DPL = Priv Lvl of Caller

7. Edge- vs. Level-Triggered Interrupts Edge triggered interrupts signal as a one shot event! Level triggered interrupts are signaled as long as line is raised low high low high Edge triggered Level triggered

8. Interrupt Controller: APIC Interrupt Sources Locally connected device (LINT0, LINT1) 8259A PIC (LINT0) other CPU (Bus) IO-APIC (Bus) Timer Performance Monitor Thermal Monitor local APIC CPU APIC bus / System bus LINT0 LINT1 Sensor Controller

9. Interrupt Controller: APIC Interrupt Sources Locally connected device (LINT0, LINT1) 8259A PIC (LINT0) other CPU (Bus) IO-APIC (Bus) Timer Performance Monitor Thermal Monitor local APIC CPU APIC bus / System bus LINT0 LINT1 8259A PIC … 0 15 NMI

10. Interrupt Controller: APIC Interrupt Sources Locally connected device (LINT0, LINT1) 8259A PIC (LINT0) other CPU (Bus) IO-APIC (Bus) Timer Performance Monitor Thermal Monitor local APIC CPU APIC bus / System bus LINT0 LINT1 local APIC CPU LINT0 LINT1

11. Interrupt Controller: APIC Interrupt Sources Locally connected device (LINT0, LINT1) 8259A PIC (LINT0) other CPU (Bus) IO-APIC (Bus) Timer Performance Monitor Thermal Monitor local APIC CPU APIC bus LINT0 LINT1 IO APIC

12. Interrupt Controller: APIC Interrupt Sources Locally connected device (LINT0, LINT1) 8259A PIC (LINT0) other CPU (Bus) IO-APIC (Bus) Timer Performance Monitor Thermal Monitor local APIC CPU System bus LINT0 LINT1 IO APIC PCI-BUS

13. Interrupt Controller: APIC Interrupt Sources Locally connected device (LINT0, LINT1) 8259A PIC (LINT0) other CPU (Bus) IO-APIC (Bus) Timer Performance Monitor Thermal Monitor local APIC CPU APIC bus / System bus LINT0 LINT1  Timer  Periodic  one shot  Performance Monitor  PMC overflow  one shot PMC event  Thermal Monitor

14. Once upon a time there was a PIC 8259 A xx Mask Interr. 01234567 CPU Interrupt Enable Flag acknowledge Interrupt Int Nr. Signals: INTR = Interrupt Request INTA = Interrupt Acknowledge

15. Once upon a time there was a PIC 8259 A Mask Interr. 01234567 CPU Interrupt Enable Flag Mask Interr. 0808 1919 2 10 3 11 4 12 5 13 6 14 7 15 Control lines

16. APIC: Interrupt Acceptance and Priorities In Service Register Interrupt Request Register Task Priority Register LVT LINT0 LINT1 PMC Thermal Timer Interrupt Command Register Vector system bus < Vector / 16 Accept Vector CPU