1. L. Ratti a,b, M. Dellagiovanna a, L. Gaioni a,b, M. Manghisoni b,c, V. Re b,c, G. Traversi b,c, S. Bettarini d,e, F. Morsani e, G. Rizzo d,e a Università degli Studi di Pavia b INFN Pavia b Università degli Studi di Bergamo c Università degli Studi di Pisa d INFN Pisa Total ionizing dose effects in deep N-well CMOS MAPS SuperB Workshop IX June 16-20 2009 Perugia, Italy

2. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX Outline Motivation DUTs and test procedures Experimental results Conclusion and future plans Degradation in charge sensitivity and equivalent noise charge in DNW-MAPS Single device (NMOS transistors and diodes) characterization DNW-MAPS with different features, single NMOS transistors, DNW diodes 60 Co  -rays, 100°C/168h annealing First investigation on radiation hardness properties of deep N-well monolithic sensors Preliminary results from test of heavily irradiated DNW MAPS

3. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX Motivation In the experiments at the future high luminosity colliders and B-factories (ILC, SuperB) need for fast, highly granular, low material budget particle trackers may feature minimal readout electronics  small pitch, high spatial resolution CMOS monolithic active pixel sensors (MAPS) may provide improved position and momentum resolution based on collection of diffusing charge  may be thinned down to a few tens of μm, low multiple scattering Depending on the experiment characteristics, MAPS may be required to withstand a total ionizing dose from a few 10 krad to a few Mrad per year A recently proposed approach takes advantage of CMOS triple well structures to improve the readout speed of MAPS sensors through pixel level sparsification and time stamping

4. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX In triple-well CMOS processes a deep N-well is used to isolate N- channel MOSFETs from substrate noise These features were exploited in the development of deep N-well (DNW) MAPS devices A DNW is used to collect the charge released in the substrate A classical readout channel for capacitive detectors is used for Q-V conversion  gain decoupled from electrode capacitance NMOS devices of the analog section are built in the deep N-well Using a large detector area, PMOS devices may be included in the front-end design  charge collection inefficiency depending on the relative weight of the DNW area with respect to the area of all the N-wells (deep and standard) Deep N-well MAPS Deep N-well structure NMOS PMOS Buried N-type layer P-well Standard N-well P-substrate + + + + - - - -

5. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX DUTs and test procedures 130 nm CMOS DNW-MAPS standalone readout channel (integrated inside the DNW but not connected to it) MAPS with different sensor area (900  m 2, 1500  m 2 ) 130 nm single NMOSFETs devices with different channel length and width pn diode structures n + /p, n + /p-well/niso, p-well/niso/p (same as DNW sensor), p + /n-well 60 Co  -ray, 100°C/168h annealing 1.1 Mrad maximum integrated dose, 12 rad/s dose rate, all devices biased as in real application Apsel2T test chip (t p =0.5, 1, 2 μs)

6. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX DUTs and test procedures 50  m pitch, also including threshold discriminator and latch (not shown)

7. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX Effects on charge sensitivity DNW-MAPS (900  m 2 sensor area)Standalone readout channel Charge sensitivity G Q decreases with dose, slight recovery after annealing

8. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX Effects on charge sensitivity in the preamplifier Circuit simulations Threshold voltage shift in the preamplifier feedback NMOS and leakage current from the detector

9. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX Effects on charge sensitivity in the preamplifier Gate dimensions [  m/  m]  V th [mV] 1000/0.130 1000/0.35-2 600/0.35-4 20/0.13-2 20/0.20-3 20/0.35-3 10/0.13-3 10/0.35-5 0.18/10-20  V th in 130 nm NMOS devices after 1100 krad TID Hole buildup in field oxide over the junction and increase of the trap density at the Si/SiO 2 interface Charge trapping in the STI and at the STI/silicon interface (radiation induced narrow channel effect, takes place in both N and P channel devices, see IEEE TNS vol.52, no.6, pp.2413-2420) DNW diode (~30000  m 2 area)

10. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX Effects on charge sensitivity in the shaper k 1 >1 accounts for radiation induced transconductance increase, k 2 <1 for gain-bandwidth product reduction From calculation

11. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX Effects on equivalent noise charge (ENC) channel thermal noise in the input device flicker noise in the input device parallel noise in the feedback MOSFET Standalone readout channel affected by ionizing radiation

12. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX Standalone readout channel (1100 krad) After irradiation, ENC is mainly determined by 1/f noise contribution in the preamplifier input device and parallel white noise in the preamplifier feedback MOSFET Effects on equivalent noise charge

13. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX TID, flicker noise and STI oxides STI Already observed in 130 and 90 nm NMOS at much higher doses (10, 100 Mrad(SiO 2 ), see IEEE TNS vol.54, no.6, pp.2218-2226) Likely to be responsible for low frequency noise increase in preamplifier input device mfmf 12 Flicker noise contribution from parasitic MOSFETs turned on by charge buildup in STI oxides

14. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX Effects on equivalent noise charge channel thermal noise in the input device flicker noise in the input device parallel noise in the feedback MOSFET affected by ionizing radiation parallel noise in the detector leakage DNW-MAPS (900  m 2 area)

15. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX Tests with heavy TID: DUTs and procedures 130 nm CMOS DNW-MAPS M1: 3x3 matrix, collecting electrode with a main body and satellite N-wells (670 μm 2 ) DNW diode test structure including devices with different area 60 Co  -ray, 100°C/168h annealing ~10 Mrad maximum integrated dose, 9 rad/s dose rate, MAPS biased as in real application Apsel3T1 test chip (t p =200, 400 ns) M2: 3x3 matrix, T-shaped collecting electrode (880 μm 2 ) M3: 8x8 matrix (half featuring M1-like cells, the other half M2- like cells) with 8-parallel digital readout Particular care is devoted to investigation of the charge collection properties of the sensor (tests with 55 Fe, 90 Sr, infrared laser)

16. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX Effects on charge sensitivity and ENC Charge sensitivity G Q decreases with dose; decrease after 900 krad is compatible with the decrease observed in Apsel2T after 1.1 Mrad ENC increases with dose; increase after 900 krad is larger than the increase detected in Apsel2T after 1.1 Mrad at similar peaking times (due to different W, finger number and drain current in the input device) Significant recovery after 100ºC/168h annealing cycle

17. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX Infrared laser tests Slight decrease in collected charge (~13% in the peak value) after 3.3 Mrad 60 Co γ-ray dose Before irradiation 3.3 Mrad M1 sensor, t p =400 ns

18. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX TID tests (  -rays up to 1.1 Mrad) have been performed for the first time on DNW-MAPS, conceived for particle tracking in HEP experiments at the next high luminosity colliders Conclusion and future plans Change in charge sensitivity of the order of 10% mainly due to radiation induced narrow channel effects in some critical points of the preamplifier and the shaper and to leakage current from the detector More significant increase in equivalent noise charge mainly due to 1/f noise increase in the preamplifier input device and in the parallel noise contribution from the preamplifier feedback NMOS and from the detector in order to avoid excessive flicker noise increase, use of radiation hard techniques (e.g. ELT transistors) may be required parallel noise issue may be addressed by using smaller peaking times Tests with higher TIDs (up to ~10 Mrad) on a more recent version of the DNW-MAPS for SuperB presently under way Next step: investigation of bulk damage effects on the collecting electrode properties

19. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX Backup Slides

20. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX Estimated 1/f noise increase in the preamplifier input device

21. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX Flicker noise in irradiated NMOS devices G S D S i,main S i,lat g m,main v gs g m,lat v gs main deviceparasitic device S e,post Postirradiation device model Postirradiation flicker noise contribution

22. L. Ratti, “TID effects in DNW CMOS MAPS”, SuperB Workshop IX Parallel noise contribution From the amplifier feedback MOSFET From the leakage current Overall contribution