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Tutorial on Verilog HDL
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Introduction Traditional way for logic design
Based on using Boolean logic equation This is what we had learned in the logic design course First, Boolean logic equations should be written manually Second, the corresponding schematic could be drawn Both are error-prone, and tedious 2
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Introduction Another traditional way for logic design
Schematic-based design method This is what we had done in the logic design lab. course First, hierarchical RTL structure and corresponding behavior are thought by designers All Boolean logic equations are written manually Second, the corresponding schematic are drawn using a schematic editor Still, error-prone, and tedious
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Introduction A new way for logic design
HDL(Hardware Description Language)-based design method This is what we are studying in this course First, hierarchical RTL structure and corresponding behavior are thought, and described in HDL by designers Then, all Boolean logic equations are generated automatically Corresponding schematic are also generated automatically Much less error-prone, and tedious 4
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Verilog HDL History Developed in Silicon Valley in by Philip Moorby Became the property of Gateway Design Automation, Inc, which was later acquired by Cadence Design Systems Later, Cadence opened the language to the public Finally, IEEE standardized the language in 1995, i.e. IEEE Standard 1364 5
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Verilog HDL Module Everything in Verilog are modules
E.g. logic gates, FF’s, ALU’s, CPU’s, etc are all Verilog modules Every modules except testbench module must have I/O for communicating with the environment Every modules also must have their body part for describing their inside 6
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Verilog HDL Module I/O BODY module mypc (…); input ….. ; output …….;
endmodule BODY I/O 7
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Verilog HDL Module module mypc (…); input ….. ; output …….;
‘include …….. endmodule 8
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Verilog HDL Module 9
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Verilog HDL Identifier in Verilog
It must be composed of letters, digits, dollar signs($), and underscore characters(_) only It must start with a letter or underscore No spaces are allowed inside an identifier Upper and lower case letters are distinguished, e.g. Verilog is case-sensitive Reserved keywords cannot be used as identifiers 10
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Verilog HDL Identifier Examples
Legal identifies: Counter_4Bit, Mux_4_To_1, ALU, alu, UART_Transmit, Receiver, MyPC, _4Bit, Mymodule, My$Maker, etc Illegal identifiers: module, 4BitAdder, My PC, Counter!, etc 11
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Verilog HDL Comments in Verilog Two types of comments
One-line comments start with two slashes(//) and terminate at the end of the line Block comments start with a slash and an asterisk(/*) and terminates with an asterisk and a slash(*/). They can extend to multiple lines and may contain nested one-line comments 12
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Verilog HDL Typical comments in Verilog 13
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Verilog HDL Module interface Two parts for module interface
PORT LIST: it contains only the names of the ports, which are specified in brackets after the module name PORT DECLARATIONS: All ports listed in the port list are described here in detail. The declaration specifies the direction of the data flow through the port and its width 14
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Verilog HDL Module interface example 15
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Verilog HDL For describing module body part
Three different coding styles Behavioral Dataflow Structural 16
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Verilog HDL For describing module body part
Three different coding styles Behavioral 17
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Verilog HDL For describing module body part
Three different coding styles Dataflow 18
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Verilog HDL For describing module body part
Three different coding styles Structural 19
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Verilog HDL For describing module body part
Three different coding styles Behavioral Dataflow Structural 20
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Verilog HDL Most typical way for describing the body part of complex modules Behavioral, dataflow, or structural? Mixed 21
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Verilog HDL For describing module body part
Three different coding styles examples See the interactive EVITA_VERILOG tutorial 22
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Verilog HDL Signals in electronic systems Most important objects
Signals always carry some kind of information Everything in electronics is about receiving, transmitting, and sending signals 23
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Verilog HDL Signals in Verilog HDL
Same role as variables in SW languages Can have only four values, 0, 1, unknown (‘x’ or ‘X’) and high impedance (‘z’ or ‘Z’) 24
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Verilog HDL Logic operations on four-value signals
See the interactive EVITA_VERILOG tutorial 25
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Verilog HDL Classes of signals
NET: It represents physical connection btw hardware elements. It does not have any storage capacity and its value is either determined by the value of its driver (signal source) or by high-impedance REGISTER: It can store value even when disconnected. The assigned value is kept until a new value is assigned. Therefore, it is more like variable in SW languages. Verilog register is NOT the register made of FF’s 26
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Verilog HDL NET Class Most signals in a system can be classified as nets because they connect devices and are driven by device outputs NET is not a Verilog keyword, but the name of a class of signals, consisting of several types wire and tri: Most frequently used. Two different names for indicative purpose only. wire for single-driver nets, and tri for multiple-drivers nets. wand/triand and wor/trior: For wired ‘and” and ‘or’ operations. Two different names for indicative purpose only 27
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Verilog HDL Signal specification
Before anything can be used in a Verilog specification, it must be declared first Two groups of signals, external and internal For internal signal declaration A keyword denoting the type of the signal is followed by a signal name (ex: reg sig1;) Several signals of the same type can be declared together by using commas (ex: wire sig1, sig2, sig3;) 28
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Verilog HDL Signal specification (Cont’d)
Scalar signals and vector signals For vector specification For declaring a vector, the index must be placed btw the type of signal and its identifier EX: wire [15:0] databus; For more examples, see interactive EVITA_VERILOG tutorial 29
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Verilog HDL Signal specification (Cont’d)
Internal signals are declared and used inside a module, and not accessible from its outside For communicating with the outside world, external signals should be used External signals are declared as module ports 30
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Verilog HDL Signal specification (Cont’d)
Two features characterize ports; the width of each port and the direction of the data flow through the port Each port can have any of three directions; input: The data is read by the module from the environment through input ports; it is not possible to write to such ports within the module output: The data is sent by the module to the environment through output ports; reading by the module from them is illegal inout: The data is either read from or written to; also called bi-directional See the interactive EVITA_VERILOG tutorial for an example 31
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Verilog HDL Signal specification (Cont’d) The specification of ports
See the interactive EVITA_VERILOG tutorial for an example 32
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Verilog HDL Signal specification (Cont’d) Registered outputs
Verilog Standard assumes all ports to be nets of the type wire However, in some cases a type wire is not enough because they must be driven at all times; otherwise they immediately go to a high impedance state The type reg can hold the value until a new assignment is given Only output ports can be registers. The keyword reg is used to start the declaration See the interactive EVITA_VERILOG tutorial for an example 33
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Verilog HDL Structural View of a System
See the interactive EVITA_VERILOG tutorial 34
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Verilog HDL Expressions Outputs <= Transformations (Inputs)
Transformations are performed by expressions Transformations: Constructs that combine operands with operators to produce a result In Verilog, an operator can have one, two, or three operands There is a legal set of operand types that can work with the operator 35
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Verilog HDL Operands Operands can be of different types, and must be compatible with the operators Operands examples Nets or registers by their names (ex: Radius, in1, DataBus, etc) Constant values of different types (ex: 1.3e7, 127, 4’b1001, etc) For vectors, part-select or bit-select operands; for memories, part-select operands (ex: DataBus[7:4], DataBus[0], etc) A call to a function as an operand returns a value compatible with the operator (ex: CircleArea(Radius), etc) 36
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Verilog HDL Integer Constants Integer constants are decimal by default
Ex: 123, -145, etc Ex2: -10 //internally represented as two’s complement to decimal 10 For non-decimal numbers They must be started with a single quote character (‘) and a letter denoting the base; h or H for hex., o or O for octal, and b or B for binary Any value specified this way is treated as an unsigned integer Ex: ‘h80AF, ‘o7123, ‘b , etc The size of the integer constant is determined by the compiler, but must be at least 32 bits 37
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Verilog HDL Integer Constants (Cont’d)
Verilog allows the use of sized constants, which are preceded by a positive integer value denoting the number of bits Ex: 4’d4, 8’b , 8’b1 (=8’b ), 8’h1 (=8’h ), etc Entering a size of a decimal value, use the letter d or D to specify the base Ex: 4’d4 // decimal 4 to be written on 4 bits instead of default, e.g. 32 bits -8’d10 // internally represented as two’s complement to decimal 10 and // written on 8 bits 38
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Verilog HDL Integer Constants (Cont’d) ‘?’ character
Could be used as a digit instead of ‘z’ for readability Cannot be used with decimal numbers Ex: 8’h1? // equivalent of ‘8h0001zzzz 2’b1? // equivalent of ‘2b1z ‘x’(‘X’) and ‘z’(‘Z’) characters Represent ‘unknown’ and ‘high impedance’ value, respectively Ex: 4’b01xx, 8’h1x (=‘8h0001xxxx), ‘hx (= default-bit unknown number), 8’hxx (= 8-bit unknown number) 39
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Verilog HDL Integer Constants (Cont’d) ‘_’ character Left padding
Could be used anywhere inside the number except as the first character Readability only Ex: 16’b1001_1100_1110_0001, 197_832_001, etc Left padding It occurs when the size of the unsigned number is smaller than the specified constant size Ex: 8’b0 (= ‘8b ), 8’b1 (=8’b ), etc If the leftmost but in the constant is ‘x’ or ‘z’, then the padding will be done with ‘x’ or ‘z’, respectively Ex: 8’bx (= ‘8bxxxxxxxx), 16’hx10 (=16’hxxxxxxxx ), etc 40
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Verilog HDL Bit-Select and Part-Select Operands
Use the select operand for a part of a vector net or register bit-select operand for single-bit selection, and part-select operand for multiple-bits selection Example: reg [7:0] DataBus; Bit-Select: DataBus[0], DataBus[1], …, DataBus[7] Part-Select: DataBus[5:2], DataBus[7:1], DataBus[7:6], etc Selecting bits or parts of real or realtime registers is not allowed 41
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Verilog HDL Arithmetic Operators
Addition (‘+’), subtraction (‘-’), multiplication (‘*’), division(‘/’) Modulo operation (‘%’) They treat differently operands of register and integer types, i.e. register type is treated as unsigned and integer type is treated as signed 42
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Verilog HDL Relational Operators
Less than (‘<’), greater than (‘>’), less than or equal to (‘<=’), greater than or equal to (‘>=’) The result of the expression is 0 if the specified relation is false or 1 if it is true If any bit of any of two operands is unknown or high impedance, then the results of any relation operators will be unknown (x). If one of the operands has fewer bits than the other, it will be left padded with zeros The relational operators have lower precedence than arithmetic operators See some examples with the interactive EVITA_VERILOG tutorial 43
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Verilog HDL Logical Operators Three classes of logical operators
Logical operators: take two operands of arbitrary length, perform a logical comparison, and give a single bit result Bit-wise operators: take two operands of arbitrary length, and apply a logical operation on a single bit on pairwise fashion. The result has the same number of bit as the longer of the two operands (the shorter is left padded) Reduction operators: take only one vector operand and yield a single bit result by applying the logical operation to all bits of the operand See some examples with the interactive EVITA_VERILOG tutorial 44
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Verilog HDL Shift Operators
Shift left (<<) and shift right (>>) Empty bits are filled with zeros during the shift operation No rotation operators in Verilog See some examples with the interactive EVITA_VERILOG tutorial 45
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Verilog HDL Concatenation and Replication Operators
Concatenation ({,}) appends multiple operands to form one vector Ex: NewVec = {Data[3:2], Data[5], Reg1} Replication operators is an extension of concatenation Ex: {3{Data[1:0]}} is same as {Data[1:0], Data[1:0], Data[1:0]} See more examples with the interactive EVITA_VERILOG tutorial 46
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Verilog HDL Continuous Assignment
Two main types of assignments in Verilog continuous assignment procedural assignment The syntax of continuous assignment Reserved word assign Optional delay declaration The left-hand side part, called the target, can be a net. Registers not allowed. Assignment symbol ‘=‘ The right-hand side part is an expression, which operands can be of any legal type (constants, net. Registers, function calls, etc) See some examples with the interactive EVITA_VERILOG tutorial 47
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Verilog HDL Implicit Continuous Assignment
See some examples with the interactive EVITA_VERILOG tutorial 48
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Verilog HDL Conditional Assignment
Conditional operator has three operands 1st operand: condition for the execution of one of two 2nd operand: the operand will be assigned if the condition is true 3rd operand: the operand will be assigned if the condition is false If the condition is ‘x’, both operands are evaluated and their values compared bit by bit. If they are same, the value is assigned to the target, but it they are different, an ‘x’ value is assigned to that bit of the target net. Ex: assign Out = Sel ? In1 : In0 ; 49
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Verilog HDL Conditional Assignment (Cont’d)
A conditional assignment is executed whenever any of the operands on the right-hand side changes its value, i.e. there is an event on it Multiple conditional assignments are executed concurrently 50
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Verilog HDL Delays See some examples with the interactive EVITA_VERILOG tutorial 51
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Verilog HDL Registers Register: An abstraction of a data storage element, i.e. Verilog equivalent of a variable in C or Pascal There are several types of registers, reg, integer, real, time and realtime See some examples with the interactive EVITA_VERILOG tutorial 52
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Verilog HDL Vectors and Arrays
Register vectors of the type reg can be declared in a similar way to net vectors A vector can consist of elements of the reg type only Ex: reg [7:0] MyData; MyData[5] refers to the 5th bit of the vector Other type of Verilog registers is array which is not available for nets An array can consist of elements of the reg, integer or time types Ex: reg MyData [7:0]; MyData[5] refers to the 5th element of the array A vector can be assigned a new value in a single assignment statement, but an array could not 53
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Verilog HDL Memories A memory is an array of vectors
Ex: reg [7:0] MyMem [3:0]; A memory is referenced only word by word If a single bit or a part of a word has to be referenced, the complete word must be first copied into a temporary register, and then the required bits can only be accessed from this register Ex: TempReg = MyMem[2]; Partselbit = TempReg[2]; Ex: MyMem[0], MyMem[1], MyMem[2], MyMem[MyMem[3]]; 54
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Verilog HDL Parameters The syntax of parameters declaration
The parameter keyword; The name of the parameter; Value of the parameter specified after the ‘=‘ symbol; A semicolon (;) terminating the line Two or more parameters can be specified on one declaration by sing commas (,) seperating the name-value pairs Parameters are most often used for representing delay, or size of objects (width of buses or vectors) See some examples with the interactive EVITA_VERILOG tutorial 55
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Verilog HDL Behavioral Description
All behavioral specifications must be encapsulated in one or more blocks defined as procedure statements Blocks are executed concurrently, similar to continuous assignments or instantiated modules There are two types of blocks, initial blocks and always blocks Each Verilog module may have any number of blocks of both types but they cannot be nested If a block contains multiple statements, they must be grouped using begin and end pair (for sequential execution) or fork and join pair (for concurrent execution) 56
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Verilog HDL Behavioral Description
See some examples with the interactive EVITA_VERILOG tutorial 57
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Verilog HDL Assignments in Blocks Procedural assignments
The target of the assignment (left-hand side of the statement) must be a register (reg, integer, real or time), a bit or part of a vector of registers. It cannot be a net There is no assign keyword preceding the assignment It must be specified within a block (initial or always) A procedural assignment changes the value of the target register only when the assignment is executed according to the sequence of operations in the block Blocking assignment, and non-blocking assignment See some examples with the interactive EVITA_VERILOG tutorial 58
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Verilog HDL Delays in Procedural Assignments
The most popular method of specifying delays is using regular delay of assignments. Each delay specifies the time that has to pass between execution of the preceding operation and the current one See an example with the interactive EVITA_VERILOG tutorial 59
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Verilog HDL Block Execution
See an example with the interactive EVITA_VERILOG tutorial 60
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Verilog HDL Conditional Operations
If (expression_true) true_statement; {else false_statement;} true_statement or false_statement can be a single statement or a block of statements enclosed with the begin end delimiters See an example with the interactive EVITA_VERILOG tutorial 61
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Verilog HDL Multiple Choice
The expression that is specified within parenthesis after the keyword case is checked and compared one by one to the values specified below The first statement that matches the actual value of the expression will be executed. If none of the expression values matches the expression, the default branch executes case compares all bits as they are; casez interprets ‘z’ as a ‘don’t care’; casex interprets ‘z’ and ‘x’ as a ‘don’t care’ Ex: ‘zx’ matches any two-bit value in casex, any two-bit value ending with ‘x’ (i.e. ‘0x’, ‘1x’, ‘xx’ or ‘zx’) in casez, and only ‘zx’ in case statement See an example with the interactive EVITA_VERILOG tutorial 62
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Verilog HDL Loops There are four kind of loop constructs, forever, repeat, while and for The forever loop is the simplest and repeats its contents forever The repeat loop executes its contents a fixed number of times The while loop specify a condition for execution The for loop is the most flexible and it specifies the initial condition, terminating condition, and the assignment that is updating the control variable in each iteration See an example with the interactive EVITA_VERILOG tutorial 63
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Verilog HDL Timing Control in Behavioral Blocks
Inter-assignment delay vs. intra-assignment delay See an example with the interactive EVITA_VERILOG tutorial 64
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Verilog HDL Events Delays are not the only way of explicit timing control. Events are another one Events are changes in nets or registers An event control statement is specified with that symbol, followed by the name of a register or net Event control construct can be located in the same place as delays, i.e. either within or before a statement Events with the negedge and posedge keywords See an example with the interactive EVITA_VERILOG tutorial 65
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Verilog HDL Wait Statement
The wait statement begins with the keyword wait, followed by a logical condition specified in the parenthesis and statement whose execution depends on the result of the condition wait (enable) statement; See an example with the interactive EVITA_VERILOG tutorial 66
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Verilog HDL Sensitivity List
Whenever a statement is activated by an event on a signal, it is called sensitive to that signal Verilog allows specifying statements that are sensitive to any number of signals. Such signals are separated by the or keyword. It is called the sensitivity list In particular, event control and sensitivity list are most often used in the always blocks 67
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Verilog HDL Sensitivity List
See an example with the interactive EVITA_VERILOG tutorial (there is an error!!!) For modeling a rising-edge sensitive flipflop having asynchronous reset (posedge RST or posedge CLK) begin if (RST) Q <= 1’b0; else Q <= D ; end 68
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Verilog HDL Non-blocking Assignment
Non-blocking assignments introduce concurrency into the sequential statements When a non-blocking assignment is activated, the delay (specified inside the assignment) is counted in order to assign the correct value to the target. However, as the name suggests, the control is also passed to the next statement, regardless of the delay value. As a result, non-blocking assignments are executed in parallel with other statements in a block See an example with the interactive EVITA_VERILOG tutorial 69
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Verilog HDL Non-blocking Assignment (Cont’d)
Why the non-blocking assignments needed? 1st, they allow modeling multiple concurrent data transfers after a common event 2nd, the read (evaluation of the right-hand side) and write (real assignment to the target) are separated in these assignments, eliminating race condition in some assignments (like swapping value) For modeling sequential behavior such as flipflops or latches, non-blocking assignments must be used Ex: (posedge clock) Q <= D ; 70
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Verilog HDL Parallel Blocks
See an example with the interactive EVITA_VERILOG tutorial 71
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Verilog HDL Verilog Subroutines
Two types of Verilog subroutines, tasks and functions Both tasks and functions are purely behavioral pieces of code, i.e. they should be used inside behavioral blocks (initial and always) They can be used inside other subroutines as well, but some restrictions apply Local variables, registers, integers and reals can be defined both for tasks and functions, and in both cases nets cannot be defined Both tasks and functions are declared within a module and are local to the module in which they are declared In order to share task or function declarations btw different modules, a declaration must be specified in a separate file which is included in a module using the ‘include compiler directive 72
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Verilog HDL Verilog Subroutines (Cont’d)
Two types of Verilog subroutines, tasks and functions There is no restriction on the use of any timing or event controls inside a task. Therefore, tasks do execute at the time specified by the designer Using timing or event control of any type is not allowed inside functions. Therefore, any function is executed in one simulation time unit There is no limit for enabling other subroutine inside a task, i.e. a task may call another task or function Due to the restrictions on timing control, a function may not call any tasks, even if no timing control exists in that task. There is no restriction on enabling other functions inside a function The number of arguments for a task is unlimited: a task can have zero or more arguments of any type; input, output, or inout. On the other hand, tasks do not return any value by definition, but can pass values through output and inout arguments 73
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Verilog HDL Verilog Subroutines (Cont’d)
Two types of Verilog subroutines, tasks and functions Each function must have at least one input argument. They cannot have any output or inout arguments. The result of a function’s execution is always a single value, returned through the function name Due to limitations on timing control, functions refer to purely combinational code, similarly to conversions or calculations. Functions are invoked as operands in expressions Tasks are invoked as separate statements, and can support multiple goals 74
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Verilog HDL Verilog Subroutines (Cont’d) Tasks
To specify a task, follow the procedure below Define a name for the task and specify it after the keyword task but preceding the declarations. Add the endtask keyword after the code; task taskname; declarations_of_arguments; task_statements endtask Specify the code that is to be encapsulated as a task. If there is more than one statement inside, enclose it in the begin and end keywords Determine the role of each variable inside the code; inputs, inouts, outputs and local variables. Specify them before the code listing 75
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Verilog HDL Verilog Subroutines (Cont’d) Tasks Ex: task factorial;
output [31:0] OutFact; input [3:0] n; integer Count; begin OutFact = 1; for (Count=n; Count>0 ; Count=Count-1) OutFact = OutFact * Count; end endtask 76
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Verilog HDL Verilog Subroutines (Cont’d) Task invocation
taskname (list of arguments); For each input, inout, and output formal argument (i.e. specified in the task declatation), an actual argument has to be provided The actual arguments are associated with their formal counterparts in positional order Ex: task SomeTask; input a, b; output k, m; begin k = a + b; m = a – b; end endtask SomeTask (r, s, w, x); 77
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Verilog HDL Verilog Subroutines (Cont’d) Function declaration
A function starts with the function keyword, and ends with the endfuction keyword A function returns a single result that is available through the function’s invocation The result of a function is by default a 1-bit register. If a function of any other registered type is needed (either integer, real, realtime, or a vector), it must be specified in the function header The declarative part of a function may contain only declarations of inputs and local variables, i.e. no outputs or inouts are permitted Syntax: function [function_type] function_name; declarations_of_inputs; [declarations_of_local_variables]; begin behavioral_statements; function_name = expression; end endfunction 78
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Verilog HDL Verilog Subroutines (Cont’d) Function declaration Ex:
function [31:0] Factorial; input [3:0] Operand; reg [3:0] i; begin Factorial = 1; for ( i=2; i <= Operand; i = i+1 ) Factorial = i * Factorial; end endfunction function ParityCheck; input [3:0] Data; ParityCheck = ^Data; 79
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Verilog HDL Verilog Subroutines (Cont’d) Function call
Unlike task enabling which is invoked as a separate statement, function call is an expression operand Ex: function ParityOdd; input [15:0] DataVectorLong; begin ParityOdd = ^DataVectorLong; end endfunction Flags[3] = ParityOdd(RegAX); Select = ParityOdd(RegAX) & RegAX[0]; if (ParityOdd(AddressBus)) ………. 80
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Verilog HDL System Tasks and Functions
Verilog provides a set of predefined subroutines They are altogether over one hundred system tasks, grouped into several categories (e.g. display tasks, file I/O tasks, simulation/timing control tasks, etc) The system tasks and functions start with dollar sign ($) See an example with the interactive EVITA_VERILOG tutorial 81
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Verilog HDL Synthesis vs. Modeling
Synthesis is a process for automatically generating a hardware structural description from a hardware behavioral description Only the subset of Verilog language is synthesizable See an example with the interactive EVITA_VERILOG tutorial 82
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Verilog HDL A Real Circuit and Its Specification
Digital circuits and systems are either combinational or sequential Ex: module FullSyst (…….); ……. (posedge CLK) // for sequential part begin … <= …. // non-blocking assignment must be used end (…….) // for combinational part … = …. // blocking assignment must be used 83
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Verilog HDL Simple Combinational Circuits
Can be written in either structural or dataflow style Ex: 84
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Verilog HDL Combinational Blocks
Behavioral coding style for combinational circuits Ex: 85
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Verilog HDL Synthesizing Registers Ex:
(A or B or C) (posedge CLK) begin begin Y = …. ; Y <= …. ; Z = …. ; Z <= …. ; end end 86
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Verilog HDL Efficient Coding Styles
Efficient coding styles are important for many reasons We will look at these later 87
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Verilog HDL Unintended Latches
See an example with the interactive EVITA_VERILOG tutorial For avoiding unintended latches Use the default branch in case statements Assign expression or values to every output in each conditional branch Try to use default assignment in conditional functional blocks 88
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Verilog HDL Finite State Machines
States are coded and declared as parameters; this allows the use of symbolic names for the states and assigning state variables to them Ex: parameter Paid0 = 3’b000, Paid5 = 3’b001, ….. Paid45 = 3’b111; Next state (combinational) logic is specified either inside a combinational always block or a function which contains a case statement with a branch for every state. Each branch defines the next state depending on the value of the input signals 89
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Verilog HDL Finite State Machines (Cont’d)
A vending machine example: The machine accepts 5, 10, and 20 cents coins (inserting the respective coins is signaled by Coin5, Coin10, and Coin20, respectively) and releases a chocolate bar if the total value of the inserted coins is 45 (signal ChocBarOpen). No other coins are accepted and for the sake of specification simplicity no change is given PORTS INTERNAL SIGNALS STATE CODES NEXT STATE LOGIC STATE REGISTERS OUTPUT LOGIC 90
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Verilog HDL Test Bench There are two major Verilog modules, DUV(Design Under Verification) and TB(Test Bench), whose characteristics are quite different DUV is eventually manufactured into chip(s). Therefore it must be synthesizable TB is the virtual model of the real physical environment for the final product of DUV, i.e. chip(s). TB is only used in simulation TB always consists of the following elements An interface to DUV A stimuli generator that applies stimuli to DUV A monitor that monitors DUV responses to stimuli 91
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Verilog HDL Test Bench Test Bench DUV Test Bench 92
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Verilog HDL Test Bench TB Stimuli Generator DUV Monitor 93
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Verilog HDL Elements of Verilog Test Bench
Test bench modules have no ports The relationship btw the TB and the DUV is specified through component instantiation and structural-type specification Stimuli values assigned to the DUV inputs can be specified either directly in the TB module or in a separate module that is instantiated in the TB module The DUV outputs are monitored using system tasks, that are usually specified in a separate Verilog block for improved readability 94
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Verilog HDL Elements of Verilog Test Bench 95
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Verilog HDL Stimuli of Signals
For supplying the stimuli of signals to DUV in TB, use blocking assignments for all clock signals and non-blocking assignments for corresponding data signals synchronized to a specific clock 96
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Verilog HDL Monitoring Outputs 97
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