1. EGRE 6311 LHO 04 - Subprograms, Packages, and Libraries EGRE 631 1/26/09

2. EGRE 6312 HW 03 due Wednesday Add the function TO_ASCII to pkg_cnt1s.vhd in HW 03.zip. The function TO_ASCII should convert an input Hex nibble to an 8-bit ASCII byte. For example if the input is “1010” the returned value is “01000001”. Use tb_ascii_func.vhd in HW 03.zip to verify the TO_ASCII function.

3. EGRE 6313 Packages A module that can be shared across many different VHDL modules. Typically contains: –Related groups of functions and procedures. –User defined types and constants. Packages can be placed in Libraries. Libraries are repositories for VHDL units. –Packages, entities, architectures, and configurations. Collectively procedures, functions, packages, and libraries provide facilities for creating and maintaining modular and reusable VHDL programs.

4. EGRE 6314 Subroutines VHDL subroutines are either functions or procedures. –Functions: –Procedures:

5. EGRE 6315 Functions Functions compute a value bases on values of input parameters. All parameters are of mode “in” and cannot be modified by the function. –Not necessary to specify mode “in”. Functions execute in 0 simulation time, and thus cannot contain wait statements. The function parameter is an unconstrained array. i.e. If the parameter is a std_logic_vector we do not need to specify the size.

6. EGRE 6316 Procedures Signals cannot be declared within procedures. Signals can be passed into procedures as parameters. Unlike functions a procedure can modify its parameters. –Specify mode “in”, “out”, or “inout” for parameter. –Mode “in” is assumed. Procedures can make assignments to a signal that is within scope even though the signal is not on the procedures parameter list. –This is not good programming practice and should be avoided. Unlike processes variables within a procedure are not static.

7. EGRE 6317 Local function example using majority gate entity use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.all; -- This is necessary to find pkg_cnt1s use pkg_cnt1s.all; -- Make items in pkg_cnt1s available entity majority is Port ( x : in std_logic; y : in std_logic; z : in std_logic; f : out std_logic); end majority;

8. EGRE 6318 Local function example (continued) -- Architecture using local function architecture LFUNC of majority is function Lcnt1s(x: std_logic_vector) return integer is -- Use 32 bits as maximum word size variable count: integer range 0 to 32; Begin count := 0; for i in x'right to x'left loop if X(i) = '1' then count := count + 1; end if; end loop; return count; end function; signal w: std_logic_vector(2 downto 0);

9. EGRE 6319 Begin W <= X&y&z; process(w) Begin if Lcnt1s(w) > 1 then f <= '1' after 2 ns; else f <= '0' after 2 ns; end if; end process; end architecture LFUNC;

10. EGRE 63110 Same example using a global function Create a package (pkg_cnt1s.vhd) Create function gcnt1 in package body. Declare function gcnt1s in package to make it visible. In VHDL code that uses function specify that package will be used. Call function in architecture.

11. EGRE 63111 Package Pkg_cnt1s.vhd -- Package containg func.vcd V 1.3 8/3/08 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; package pkg_cnt1s is function gcnt1s(x: std_logic_vector) return integer; end pkg_cnt1s; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; end function; end pkg_cnt1s;

12. EGRE 63112 package body pkg_cnt1s is --------------------------------------------------------------- -- Function: gcnt1s - Global function to count #1's in x -- Maximum size of x is 32 bits. ---------------------------------------------------------------- function gcnt1s(x: std_logic_vector) return integer is -- Use 32 bits as maximum word size variable count: integer range 0 to 32; begin count := 0; for i in x'right to x'left loop if X(i) = '1' then count := count + 1; end if; end loop; return count; end function; end pkg_cnt1s; Package Pkg_cnt1s.vhd (continued)

13. EGRE 63113 Majority.vhd using global function. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.all; -- This is necessary to find pkg_cnt1s use pkg_cnt1s.all; -- Make items in pkg_cnt1s available entity majority is Port ( x : in std_logic; y : in std_logic; z : in std_logic; f : out std_logic); end majority;

14. EGRE 63114 -- Architecture using global function in pkg_cnt1s.vhd architecture GFUNC of majority is signal w: std_logic_vector(2 downto 0); begin W <= X&y&z; process(w) begin if Gcnt1s(w) > 1 then f <= '1' after 2 ns; else f <= '0' after 2 ns; end if; end process; end architecture GFUNC;