1. PArISROC Photomultiplier Array Integrated in Sige Read Out Chip Selma Conforti Frédéric Dulucq Christophe de La Taille Gisèle Martin-Chassard Wei http://omega.in2p3.fr

2. 12 septembre 2008 Gisèle Martin-Chassard 2 Contents  OMEGA presentation  PMm2 project  PARISROC description  Simulation results  Conclusion

3. 12 septembre 2008 Gisèle Martin-Chassard 3 Orsay Micro-Electronics Group Regional “pole” for micro-electronics Serves 4 labs from Paris-south (CSNSM, LAL, LLR, IPNO). A strong team of 10 ASIC designers… –A team with critical mass –Expertise in low noise, low power, high level of integration ASICs …Within an electronics department of 55 people –Support for tests, measurements, PCBs… SPIROC Analog HCAL(SiPM) 36 ch. 32mm² June 07 HARDROC Digital HCAL (RPC, µmegas or GEMs) 64 ch. 16mm² Sept 06 SKIROC ECAL (Si PIN diode) 36 ch. 20mm² Nov 06 MAROC Luminometry (MAPMTs) 64 ch. 16mm² june 05

4. 12 septembre 2008 Gisèle Martin-Chassard 4 PMm2 : “Innovative electronics for array of photodetectors used in High Energy Physics and Astroparticles”. R&D program funded by French national agency for research (ref. ANR-06-BLAN-0186) (LAL, IPNO, LAPP and Photonis) (2007-2010) Application : large water Cerenkov neutrino (more generally: exp. with large number of PMs) PMm 2 project (I)

5. 12 septembre 2008 Gisèle Martin-Chassard 5 The project proposes to segment the very large surface of photodetection in macro pixels made of 16 photomultiplier tubes connected to an autonomous front-end electronics. Replace large PMTs (20”) by groups of 16 smaller ones (12”) with central ASIC : –Independent channels –charge and time measurement –water-tight, common High Voltage –Only one wire out (DATA + VCC) Target : –1pe efficient –Triggerless –1ns time resolution –High granularity –scalability –Low cost PMm 2 project (II)

6. 12 septembre 2008 Gisèle Martin-Chassard 6 Complete front-end chip with 16 channels Sent in fabrication in June 2008 Technology : AMS SiGe 0.35  m Characteristics : –16 inputs preamplifier Variable gain :1  8 (4bits) (common on 16 channels) PMTs gain adjustment by a factor 4 (8 bits) (channel by channel) Input dynamic range : 0  300 pe (0  50pC) Good linearity (1%) –16 trigger outputs: Fast shaper (  =15ns) Low offset discriminator Threshold provided by common 10bit DAC +4bit DAC/ch. (1/3 pe) “OR” of 16 triggers output –1 digitized and multiplexed charge output : Dynamic range : 0  300 pe Slow shaper with variable shaping time (  =50ns,100ns,200ns) SCA with depth 2 PArISROC description (I)

7. 12 septembre 2008 Gisèle Martin-Chassard 7 Coarse time measurement (timestamp) : –24-bit counter @ 10MHz –Step : 100ns 12-bit ADC for charge and fine time measurement : –Wilkinson type ADC –T&H on slow shaper for charge measurement –T&H on TDC ramp (100ns) for fine time measurement –2 discriminators with 12 bit ramp (100  s) as threshold Serialization of digital output information : Channel number - time stamp – charge - fine time 4bits24bits 12bits 12bits PArISROC description (II)

8. 12 septembre 2008 Gisèle Martin-Chassard 8 PArISROC architecture CRRC2 Slow Shaper (50, 100, 200 ns) Fast Shaper (15ns) 16 charge inputs 1 mux. charge output Track & hold Discri Variable Gain Amplifier (1-5) Gain Correction (8bits) DAC 10 bits variable delay Bandgap Vref SSH Vref FSH Vref SSH Channel 1 Channel 16 Read Hold ADC discri 24 bits counter 10MHz Threshold DAC 4 bits 16 Trigger outputs OR 1 OR output Track & hold ADC discri 12 bit TDC ramp 12 bit ADC ramp ADC conversion 40MHz Read-out 10MHz registers Serialized data out (digitized charge and time) Digital part SCA management

9. 12 septembre 2008 Gisèle Martin-Chassard 9 one channel analog part 50  ext 4-bit DAC Threshold 10-bit DAC Trigger Output Discri. x1 Ramp ADC Internal read Ramp TDC T&H PA FSH SSH VARIABLE DELAY  input signal :  0 to 300 pe  0 to 50 pC  PM’s Gain=10 6 (1pe=160 fC) Ii= 0 to 10mA Time output Charge output OR ext. Hold  Ramp TDC, Ramp ADC and 10-bit DAC common to all channels Auto-trig Adjustable and variable gain amplifier G= 1-5 Adjust = 1-4

10. 12 septembre 2008 Gisèle Martin-Chassard 10 PMT gain adjustment Cf may be changed to adjust the photomultiplier gain channel by channel (Typical value is 0.5pF) It can be adjusted by a factor of 4 (from 125fF to 2pF by step of 17fF) Preamplifier output for the same input charge and various Cf Cf= 1pF to 2pF Cf= 1pF, 0.5pF, 0.25pF PA Cf

11. 12 septembre 2008 Gisèle Martin-Chassard 11 Slow Shaper response Linearity: Qin = 0 to 50pC (0 to 300 pe) Residuals max input charge G=8-0.2% ≤R ≤0.4% 24pC (145pe) G=4 -0.2 %≤R ≤0.4% 55pC (330pe) SSH response input : 1pe noiseS/N RC = 50ns : Vout = 19 mV @ Tp = 37nsRMS = 1.6mV 11 RC = 100ns : Vout = 10 mV @ Tp= 75nsRMS = 1.2mV8 RC = 200nsVout = 5 mV @ Tp= 122ns RMS = 950uV5 LINEARITY SSH SSH 1 pe response G = 8 G = 4 RC=50ns RC=100ns RC=200ns 250 ns500 ns

12. 12 septembre 2008 Gisèle Martin-Chassard 12 ASIC simulations PA_output_G=4 Qi: 0-50 pC SSH output G=4 Qi: 0-50 pC fast shaper response at 1pe : Vout = 65 mV @ tp=7ns RMS noise = 2.3 mV SNR = 28 Fast shaper output 0ns250ns 50ns 10ns

13. 12 septembre 2008 Gisèle Martin-Chassard 13 Output DISCRIMINATOR Timewalk of 4 ns Threshold = -21mV = 50 fC = 1/3 pe Qin = 1/2 pe to 10 pe 4 ns 20ns16ns18ns 25ns50ns75ns

14. 12 septembre 2008 Gisèle Martin-Chassard 14 Preamplifier’s Characteristics :  16 inputs preamplifier  Variable gain :1  8 (4bits) (common on 16 channels)  PMTs gain adjustment by a factor 4 (8 bits) (channel by channel)  Dynamic range : 0  300 pe (0  50pC) Slow Shaper ’s Characteristics :  Variable time constant :  = 50,100, 200 ns  Linearity <1% (input dynamic range : 300pe)  SNR = 5 (RC=200ns); 8 (RC=100ns);11 (RC=50ns) Fast Shaper ’s Characteristics :  Time constant : =15 ns  SNR = 28 Discriminator ‘s Shaper ’s Characteristics :  Timewalk = 4 ns  Threshold : 50 fC= 1/3 pe Summary analog part

15. 12 septembre 2008 Gisèle Martin-Chassard 15 Digital part architecture SCA depth of 2 for time and charge measurement SCA management like FIFO Timestamp 24b counter @ 10 MHz (1.67s) 40 MHz clock for ADC + SCA management 10 MHz clock for Timestamp + Readout

16. 12 septembre 2008 Gisèle Martin-Chassard 16 Selective Read Out Only hit channels are readout Readout clock : 10 MHz Max Readout time (16 ch hit) : 100 us 52 bits of data / hit channel (all gray) Readout format (MSB first) : 4 bits channel # + 24 bits timestamp + 12 bits charge + 12 bits time

17. 12 septembre 2008 Gisèle Martin-Chassard 17 Technology : AMS SiGe 0.35m Size : 5mmX3.4mm Package : CQFP160 PArISROC layout ADC ramp 16 analogue channels Digital part TDC ramp BandgapDual DAC Bias + supply

18. 12 septembre 2008 Gisèle Martin-Chassard 18 Conclusion PARISROC : –Sent to foundry in last June –Chips come back end September Test board : –Now in layout –Available in mid October First measurement results : end 2008