1. Chapter 3. Digital Circuits

2. Logic signals Digital logic values : “0” & “1”
Called binary digit or bit
Mapping the infinite set of real analog values for a physical quantity into the finite abstract logic values “0” & “1”
Electronic logic circuits (CMOS, TTL)
LOW : 0 & HIGH : 1 → positive logic
LOW : 1 & HIGH : 0 → negative logic

3. Logic signals

4. Logic circuits and truth tables
Combinational circuits
An output only depends on the present input
Sequential circuits
An output depends on the present state (memory) and input

5. Basic logic gates

6. Digital Circuit Analysis and Design
How? . . . . . .
How?
Switching-algebra notation:
F = X·Y + X´·Y´·Z = XY + X´Y´Z

7. Real Logic Circuits’ Timing Behavior
lag (delay)

8. Logic Families History
First logic circuits based on relays
Developed at Bell Lab. in 1930s
ENIAC (1940s)
First electronic digital computer
18,000 vacuum tubes, 140,000W, 100 X 10 X 3 ft
Late 1950
Semiconductor diode and bipolar junction transistor
IC : 1960s :TTL (transistor-transistor logic) & MOS
CMOS (Complementary Metal-Oxide Semiconductor)
MOS’s principles : patented ten years before the bipolar junction tr.
Mid-1980s, high speed & lower power consumption
Vast majority of the worldwide IC market (microprocessor & memory)

9. CMOS Logic Levels CMOS logic levels driven by 5.0 volt power supply
During signal transition
Interpreted as either 0 or 1

10. MOS Transistors MOS transistors
The basic building blocks in CMOS logic circuits
NMOS (n-channel MOS) & PMOS (p-channel)
Voltage-controlled resistance
(~10 Ohm & 1 Mega Ohm ~)
[ NMOS]
[ PMOS]
leakage current : gate ↔ drain or source : 1 µA

11. Basic CMOS Inverter Circuit
[ functional behavior]
[ logic symbol]
[ circuit diagram]

12. Basic CMOS Inverter Circuit
[ switch model for CMOS inverter]
[ CMOS inverter logical operation]

13. CMOS NAND Gates

14. CMOS NAND Gates (Switch Model)

15. 3-Input CMOS NAND Gates

16. CMOS NOR Gates
n-channel ‘ON’ resistance < p-channel ‘ON’ resistance
If consider k-input gates, series of n in NAND < series of p in NOR
☞ NAND is faster than NOR

17. Fan-in
Fan-in
The number of inputs that a gate can have in a particular logic family
The series transistors limit the fan-in of CMOS gates (switching delay)
Typically to 4 for NOR gates and 6 for NAND gates
For large number of gates, cascade gates with fewer inputs
The total delay is typically less than the delay of a one-level 8-input NAND gates

18. Non-inverting gate = buffer
It is typically not possible to design a noninverting gate with a smaller number of transistors than an inverting one
[Inverter-to-inverter]

19. Buffer [ input signal ] [ output signal ]
Used to regenerate (or amplify) “weak” values into “strong” ones 5V
3.5V 5V
3.5V
[ input signal ]
[ output signal ]

20. AND gates
[Inverter]
[NAND]

21. CMOS AND-OR-INVERT (AOI) gatesQ3 Q5 Q7 Q4 Q6 Q8 Q1 Q2
Two level logic (AND – OR), one level of delay

22. Electrical behavior of CMOS circuits
Electrical aspects of CMOS circuit operation
Logic voltage levels, DC noise margin, fanout, speed, power consumption, noise, electronic discharge, open-drain outputs, three-state outputs
Data sheet
Specifying the device’s logical and electrical characteristics
Different manufactures typically specify additional parameters
Varying in how they specify the parameters
Usually showing the test circuits and waveforms

23. Data sheet (소자 제작자가 작성하여 공급)
54/74HC00
quad NAND gate

24. Electrical behavior of CMOS circuits
Static-behavior
Inputs and outputs are not changing
Logic levels and noise margin
Circuit behavior with resistive loads
Circuit behavior with nonideal inputs
Fanout
Effects of loading
Unused inputs and else
Dynamic-behavior : speed and power consumption
Transition time
Propagation delay
Power consumption

25. I/O transfer characteristic
It varies under different conditions of power-supply voltage, temperature, and output loading
VIN : 2.4 V ~ 2.6 V
→ VOUT : 1.5 V ~ 3.5 V
[Typical I/O transfer characteristic of a CMOS inverter]

26. Logic levels and noise margins
VOHmin : The minimum output voltage in the HIGH state
- 소자의 출력이 High 상태로 정상적인 동작을(적절한 전류 흐름) 하기 위해 취할 수 있는 최소 전압
VOLmax : The maximum output voltage in the LOW state
- 소자의 출력이 Low 상태로 정상적인 동작을(적절한 전류 흐름) 하기 위해 취할 수 있는 최대 전압

27. Logic levels and noise margins
VIHmin : The minimum input voltage guaranteed to be recognized as a HIGH
- 소자가 논리회로로 정확한 동작을 하기 위한 High 입력의 최소값
VILmax : The minimum input voltage guaranteed to be recognized as a LOW
- 소자가 논리회로로 정확한 동작을 하기 위한 Low 입력의 최대값

28. Logic levels and noise margins
DC noise margin
A measure of how much noise it takes to corrupt a worst-case voltage into a value that may not be recognized properly by an input
Noise margin 보다 더 큰 noise가 더해진 입력이 소자에 가해질 경우에 회로는 오동작할 수 있다.

29. Logic levels and noise margins
for the HC-series CMOS family]
VIHmin = 0.7*(0.9VCC) VILmax = 0.3*(0.9VCC)
VOHmin = 0.9VCC - 0.1V VOLmax = ground V
High state noise margin in HC-series = = 1.25 V
Low state noise margin in HC-series = = 1.25 V

30. Input currents
IIH
The maximum current that flows into the input in the High state
About 1 micro-Ampere
IIL
The maximum current that flows into the input in the Low state

31. Resistive loads (DC load)
Connected to a CMOS output
Requiring nontrivial amounts of current
Some examples of resistive loads
Transmission-line termination
One or more TTL or other non-CMOS inputs
Current-consuming devices such as LED (light-emitting diode)
When the output of a CMOS circuit is connected to a resistive load, the output behavior is not ideal as described previously

32. Circuit behavior with resistive loads
Rn, Rp
“on” state : about 100 Ω (n-channel), 200 Ω (p-channel)
“off” state : about above 1 M Ω

33. Circuit behavior with resistive loads
Vout =
100
X 3.33V = 0.43V

34. Circuit behavior with resistive loads
Vout =
667
3.33V + (5 – 3.33)
= 4.61 V V

35. Circuit behavior with resistive loads
IC manufactures specify a maximum load for the output
IOLmax & IOHmax
sinking current & sourcing current

36. Circuit behavior with resistive loads
“on” resistance from table 3-4 with a worst-case resistive load
Rp (ON) = ( VDD – VOH minT ) / IOH maxT = 165 Ω
Rn (ON) = VOL maxT / IOL maxT = 82.5 Ω

37. Circuit behavior with non-ideal inputs
If the input voltage is not close to the power-supply rail
“on” transistor may not be fully “on”
→ “on” resistance may increase
“off” transistor may not be fully “off”
→ “off” resistance may decrease

38. Circuit behavior with non-deal inputs
The slight degradation of output voltage is generally tolerable
What’s worse is that the output structure is now consuming a nontrivial amount of power
Pwasted = 5.0V · Iwasted = 8.62 mW (for VIN = 1.5V)
More serious in TTL loads rather than CMOS loads

39. Circuit behavior with non-ideal inputs
The output voltage of a CMOS inverter deteriorates further with a resistive load

40. Fanout The fanout of a logic gate IOLmaxC (Table 3-4)
The number of inputs that the gate can drive without exceeding its worst-case loading specifications (Table 3-4)
IOLmaxC (Table 3-4)
20 µA for a HC-series CMOS gate driving CMOS inputs
IImax
± 1 µA : The maximum input current for a HC-series CMOS input
Low-state fanout = 20

41. Fanout IOHmaxC HIGH-state fanout = 20 Overall fanout of a gate
- 20 µA for a HC-series CMOS gate driving CMOS inputs
IImax
± 1 µA : The maximum input current for a HC-series CMOS input
HIGH-state fanout = 20
Overall fanout of a gate
The minimum of its High-state and Low-state fanouts
DC fanout

42. Fanout Effects of loading beyond the fanout
LOW/HIGH state level changes
Propagation delay, output transition time may increase beyond spec.
Operating temperature may increase

43. Unused inputs Unused Inputs
In high-speed circuit design, it’s usually better to use (b), (c) rather than (a) since (a) increase the capacity load on the driving signal
Unused CMOS inputs should never be left unconnected
Floating input → 0 V (logic 0)

44. Etc. Current Spike Decoupling Capacitance How to Destroy a CMOS Device
Flowing from VCC to ground through the partially-on p- and n- channels when a CMOS output switches between LOW and HIGH
Showing up as noise on the power-supply and ground connections
Decoupling Capacitance
Between VCC and ground to supply current during transitions
How to Destroy a CMOS Device
ESD (electrostatic discharge)
Arcs through a dielectric to another surface with the opposite charge
Causing a short-circuit between the device’s input and output

45. CMOS dynamic electrical behavior
Speed and power consumption of a CMOS device
Depending to a large extent on dynamic characteristics of the device and its load
What happens when the output changes between states
Speed
Transition time and propagation delay

46. Transition time
The amount of time that the output of a logic circuit takes to change from one state to another
tr = rise time
tf = fall time
Ideal case (tr = tf = 0)
A more realistic approx.
Actual timing
Logic levels of inputs

47. Transition time The transition times of a CMOS output depend mainly on
“on” transistor resistance & the load capacitance (stray capacitance)
A large capacitance increases transition times
Sources of stray capacitance (capacitive load or AC load)
Output circuits
A gate’s output transistors, internal wiring, and packaging
2~10 pF
The wiring that connects an output to other inputs
About 1 pF per inch or more
Input circuits
Transistors, internal wiring, and packaging
2~15 pF per input

48. Transition time When a CMOS output drives only CMOS inputs
Stray capacitance
ⅰ) output circuit : 2~10 pF
ⅱ) wiring : 1pF / inch
ⅲ) Input circuit : 2 ~ 15 pF/inch
DC load : RL & VL
AC load : CL
When a CMOS output drives only CMOS inputs
DC load is negligible
RL = ∞ & VL = 0

49. Fall time (tf) calculation
Vcc = 5V
Vout
Vin
Rp (On resistance)=200Ω , Rn (On resistance)=100Ω , CL = 100pF
a) Fall time (tf) : Vin → high
3.5V
1.5V
‣ t < 0 , Vout = 5.0 V
‣ t > 0 , Vout = VDD • e
= 5.0 X e
= 5.0 X e V
-t/(Rn • CL)
-t/(100X100X10-12)
-t/(10X10-19)
for Vout = 3.5 , t = 3.57 nsec
Vout = 1.5 , t = nsec
‣ tf = t1.5 – t3.5 = 8.5 nsec

50. Rise time (tr) calculation
b) Rise time (tr) : Vin → low
‣ Vout = VDD • (1 – e )
= 5.0 • (1 – e )
-t/(Rp • CL)
-t/(20X10-12)
for Vout = 3.5 V , t = nsec
Vout = 1.5 V , t = nsec
‣ tr = t3.5 – t1.5 = 17 nsec
- tr > tf (twice)
If R & C → smaller, transition times → improve

51. Propagation delay tp
The amount of time that it takes for a change in the input signal to produce a change in the output signal
Vcc = 5V
Vout
Vin
mid point of transition
tPW(min)
tPHL
tPLH
[ Propagation delays for a CMOS inverter]
tPW(min) → minimum input pulse width (specified storage time)
Z > tPHL + tPLH

52. Power consumption (dissipation)
Very low static power dissipation
Static : when output is not changing
Significant dynamic power dissipation
Dynamic : when transitions occur
Overall dynamic power consumption : PD = PT + PL
PT : internal power dissipation (during transition, both n- and p- channels partially “on”)
Current flows through the transistors from VCC to ground
PL : Charging and discharging CL
PD = (CPD + CL) · VCC2 · f
CPD : Power-dissipation capacitance (20~40 pF)
CL : Capacitive load on the output
f : transition frequency of the output signal (# of transitions = 2f)
Vcc = 5V
Vout
Vin CL

53. Other CMOS input and output structures
Transmission gates
Connection of p-channel and n-channel transistors
Logic-controlled switch
Multiplexers and flip-flops
EN: High & EN_L: Low
→ A-B connecting (2~5 Ohm)
→ short propagation delay
EN: Low & EN_L: high
→ A-B disconnecting

54. Transmission gates 2-inputs multiplexer
Z = SX + SY → Inputs = X & Y, output = Z, S = Selection
For a change in the “select” input to affect the input-output path
Several nanoseconds
Propagation delay from input to output is at most 0.25 nsec

55. Transmission gates 1 on
off 1
off on 1 1

56. Schmitt-trigger inputs
VT+ = Vin positive going input change
= 2.9 V
VT- = Vin negative going input change
= 2.1 V
Hysteresis = VT+ - VT-
Better noise immunity for long rise/fall time input
[ Schmitt trigger inverter ]
VT=2.9V
[ Output by ordinary inverter ]
VT=2.5V
VT=2.1V t1 t2 t1 t2
[ Noisy, slowly changing input ]
[ Output by Schmitt-trigger ]

57. Three-state (or tri-state) output
[ CMOS three state buffer ]
EN= control (output enable)
If EN = High , A
= Low , A
OUT
High impedance state (Hi-Z)
or floating state

58. Three-state buffers [ Various three-state buffers (or drivers) ]
(a) noninverting, active-high enable (b) noninverting, active-low enable
(c) inverting, active-high enable (d) inverting, active-low enable

59. Bus using three-state buffers
Multiple data sources (P~W) can share a single bus line
Only one source talks on the bus-line at a time
Selector s1 s2 s3

60. Open-drain outputs
[ Open-drain CMOS NAND gate ]

61. Open-drain outputs Pull-up resistance
Providing passive pull-up to the HIGH level (p-channel: active pull-up)
Minimum value is determined by IOLmax
HCT-series : IOLmax = 4 mA → 5.0V/4mA = 1.25 K ohm
Should be as small as possible
for the highest speed
RC time constants
HIGH-to-LOW : 80 ohm * 100 pF = 8 ns
LOW-to-HIGH : 1.5 Kohm * 100pF = 150 ns
[ Rising and falling transitions of
an open-drain CMOS output]
[ Open-drain CMOS NAND
gate driving a load]

62. Open-drain outputs Slow rise times Why use open-drain outputs?
Useful in at least 3 applications
Driving light-emitting diodes (LEDs)
Driving multi-source buses
Performing wired logic

63. Driving LEDs = LED → 10mA for brightness
Normal CMOS (HC- and HCT-series)
→ 4 mA sink / source current
→ not proper for driving LED
74AC, 74ACT, and 74FCT CMOS families
→ sinking 24 mA
→ proper for driving LED
→ VOLmax = 0.37 V
‣ VOL + VLED + ILED • R = VDD
R =
VDD – VOL – VLED
ILED =
10mA
= 303 Ω

64. Driving LEDs
HIGH
LOW
sink current
source current
Most CMOS and TTL outputs : sink current > source current

65. Multisource buses
DATAOUT
bus
At most one control bit (Enablei) is HIGH at any time
When Enablei is HIGH and all Enablej (i ≠ j) are LOW
Datai = HIGH (logic 1) → DATAOUT = LOW (0)
Datai = LOW (logic 0) → DATAOUT = HIGH (1)

66. Wired logic
Wired-AND function

67. Wired logic [Wired 2 CMOS outputs trying
to maintain opposite logic values
on the same line]
HIGH
Typically 1~2 V (nonlogic voltages)
fighting = =
LOW
Hot chips and burns!

68. Pull-up resistors Power consumption Noise margin Switching speed
LOW
LOW
LOW
LOW ≤ ≥
LOW
LOW
LOW
LOW
[HIGH State]
[LOW State]
‣ IOL MAX = 4 mA
IR (MAX) = 4 – (2 x 0.4) = 3.2 mA
R MIN = / IR (MAX) = 1.56 KΩ
‣ IR (leak) = ( 4 x 5 uA) + ( 2 x 20 ) = 60 uA
Power consumption
Noise margin
Switching speed
R MAX = 5 – 2.4 / IR (leak) = 43.3 KΩ
‣ Pull-Up register => KΩ < R < KΩ

69. CMOS logic families 54 series 4000-series CMOS
The first commercially CMOS family
Low power assumption but slow speed
Part number of CMOS device : 74FAMnn
FAM : family mnemonic
nn : function designator
The same value of nn performs the same function
74HC30, 74AC30 → 8-input NAND gates
54 series
For operation over a wider range of temperature and power-supply voltage (military applications)

70. HC and HCT families HCT (High-speed CMOS, TTL Compatible)
Using power-supply voltage of 5 V
Can be intermixed with TTL (transistor-transistor logic) devices
HC (High-speed CMOS)
Optimized for use in systems that use CMOS logic exclusively
Using any power-supply voltage 2 ~ 6 V
Higher voltage → Higher speed
Lower voltage → Lower power consumption (CV2f)
Not quite compatible with TTL

71. HC and HCT families’ logic levels
Identical output spec.
Only input levels differ
TTL input
LOW : 0 ~ 0.8 V
HIGH : 2.0 ~ 5.0 V

72. AHC and AHCT AHC (Advanced High-speed CMOS)
AHCT (Advanced High-speed CMOS, TTL compatible)
About 2~3 times as fast as HC/HCT
Differing only in the input levels
Output characteristics are the same
Symmetric output drive
An output can sink or source equal amounts of current

73. Speed and power characteristics of CMOS families operating at 5V
00 : 2-input NAND, 138 : 3-to-8 decoder
static
CPD V2DD f
(CL= 0)
propagation delay * power consumption
: how much energy a logic gate uses
to switch its output

74. Input specifications for CMOS families

75. Output specifications for CMOS families

76. Low-voltage CMOS logic
Reducing power consumption (CV2f)
Ever-smaller transistor geometry → oxide insulation getting ever thinner
Incapable of insulating voltage potentials as “high” as 5 V
Fig Comparison of logic levels

77. Bipolar logic Basic building blocks of bipolar logic circuits
Semiconductor diodes
Semiconductor bipolar junction transistors
Bipolar logic circuits have been replaced with CMOS
Still useful to study TTL operation for the occasional applications requiring TTL/CMOS interfacing

78. Diodes Fabricated from two types of semiconductor material
p-type and n-type ≈ ≈
[ pn junction]
[ forward-biased junction]
[ reverse-biased junction]
leakage current
breakdown
[ symbol]
[ transfer char. of an
ideal diode ]
[ transfer char. of
a real diode ]

79. forward-biased diode]
Real diode behavior
[ reverse-biased]
[ forward-biased]
[ transfer char. of
forward-biased diode]
Vd (diode drop) : Typically about 0.6 V (small-signal diode)
Rf (forward resistance) : Typically about 25 Ohm
→ forward-biased diode may be considered to have a fixed drop of 0.6 V

80. Diode logic : diode AND gate

81. Diode logic : diode AND gate

82. Bipolar Junction Transistors
Three-terminal device that acts like a current-controlled switch
currents
[ npn transistor ]
[ back-to-back diode ]
[ pnp transistor ]

83. Bipolar Junction Transistors
1) Active operating region
Ib = ( Vin – 0.6 ) / R1 , Ic = β • Ib
VCE = VCC – IC • R2 = VCC – β • Ib • R2
= VCC – β (Vin – 0.6 ) R2 / R1
b : transistor gain (typically 10 ~ 100)
2) Saturation region
IC = (VCC – VCE(SAT)) / R2
VCE(SAT) : about 0.2 V
RCE(SAT) : about 50 Ohm or less
[ Common-emitter configuration ]

84. Transistor logic inverter
cut-off region
active operating region
saturation region
[ switch model ]

85. Schottky transistors
When the input of a saturated transistor is changed
Output does not change immediately
Requiring storage time to come out of saturation
Significant portion of the propagation delay
Schottky transistor
Ensuring that transistors do not saturate
Schottky diode
[ Schottky transistor not saturated ]
[ Inverter using
Schottky transistor ]
[ saturated transistor ]

86. Transistor-Transistor Logic (TTL)
Most commonly used bipolar logic family
There are many different TTL families
With a range of speed, power consumption, and other characteristics.
Examples in this section : Low-power Schottky (LS or LS-TTL)
Input logic levels
LOW : 0 ~ 0.8 V
HIGH : 2.0 ~ 5.0 V

87. Basic TTL NAND gate [ 74LS00 ] totem-pole or push-pull
Diode two input AND gate
Limiting current spike
during transitions
(Q4 & Q5 both ON)
Preventing negative
excursion on the inputs
totem-pole or
push-pull
inverting buffer amplifier

88. Basic TTL NAND gate ▶ sinking current≤
[ Fig A TTL output driving a TTL input Low ]

89. Basic TTL NAND gate ▶ sourcing current≥
[ Fig A TTL output driving a TTL input High ]

90. Logic levels and noise margins
[ Noise margin for popular TTL logic families (74LS, 74S, 74ALS, 74AS, 74F ]

91. Fanout
▶ Fanout : # of gate inputs that connected to a single gate output
74LS00 – 74LS00 (refer Fig and 3-74)
ⅰ) low state : IILmax = -0.4 mA, IOLmax (for VOLmax) = 8 mA
- low state fanout = 20
ⅱ) high state : IIHmax = 20 uA, IOHmax (for VOHmin) = uA
- high state fanout = 20
ⅲ) fanout = lesser of low/high state fanout = 20
IILmax : The maximum current that an input requires to pull it LOW
IIHmax : The maximum current that an input requires to pull it HIGH
IOLmax : The maximum current an output can sink in the LOW state while maintaining an output voltage no more than VOLmax
IOHmax : The maximum current an output can source in the HIGH state while maintaining an output voltage no more than VOHmin

92. Additional TTL gate types : NOR gate
NAND gate is the “workhorse” of the TTL family
n-input NOR gate uses more transistors and resistors → expensive in silicon area
fan-in of NOR = 5 inputs, fan-in of NAND = 13 inputs

93. TTL families’ Characteristics
[ 2-input NAND gate ]

94. CMOS/TTL interfacing but TTL can drive HCT and VHCT
VILmax
TTL can drive HCT and VHCT
HCT and VHCT can drive TTL
but
TTL cannot drive HC, VHC CMOS
[ Output and input levels for interfacing
TTL and CMOS families ]
ex) Low state DC noise margin = VIL max – VOL max = ( HC CMOS ) – 0.5 ( TTL )
= 0.85
High state DC noise margin = VOH min – VIH min = 2.7 ( TTL ) – 3.85 ( HC CMOS)
= => out of noise margin

95. Emitter-Coupled Logic (ECL)
The key to reducing propagation delay in bipolar logic family
Preventing a gate’s transistors from saturating
Schottky diodes
ECL (emitter-coupled logic) (or CML: current-mode logic)
ECL families
Small voltage swing between Low & High states
Small noise margin
Extremely fast, offering propagation delay as short as 1 ns
Gigabit Ethernet, ATM, supercomputer
Consuming much more power
Not nearly as popular as CMOS and TTL

96. Basic ECL circuit Input Low = 3.6 V & Input High = 4.4 V
Output Low = 4.2 V & Output High = 5 V ≈ ≈
(inverting) ≈ ≈
(buffering) ≈ ≈
not saturated
not saturated
Basic CML inverter/buffer circuit
with input LOW
Basic CML inverter/buffer
circuit with input HIGH