1. ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis

2. WHAT YOU GET FROM US A working late transition detector Implementation of [PS13] But without the case separation Nevertheless all counters are present But hard wired to measure the overall count only Python based PC software Automates the measurement Prints a CSV trace to standard out

3. ENVIRONMENT Virtex-4 FPGA Board is lend to students Design software: ISE webpack can be freely downloaded (after registration @ Xilinx) Includes all necessary design tools PC software Python program for collection of CSV traces Analysis with program of choice (Excel, Python, MATLAB,...)

4. YOUR TASKS Implement the case separation from [PS13] Measure three different clock duty cycles (+25, +50 and +75 steps) Analyze your measurements Calculate the different TAU values (master and slave, if applicable) for all cases and simulation runs Estimate T0 (if applicable) for all cases and simulation runs Plot each case in a separate plot and visualize the above calculated parameters Comparison plots of All cases in a single run All runs for a single case

5. EXAMPLE TRACE

6. EXAMPLE COMPARISON

7. REFERENCES PS13 - T. Polzer and A. Steininger - An Approach for Efficient Metastability Characterization of FPGAs through the Designer -19th International Symposium on Asynchronous Circuits and Systems, 2013

8. ADVANCED DIGITAL DESIGN DESIGN EXERCISE I Metastability Measurement and Analysis