1. Assembly Language Programming 4KS04

2. Introduction ALP Introduction What is Assembly Language?  Every PC has a microprocessor that manages the computer's arithmetical, logical and control activities.  Each family of processors has its own set of instructions for handling various operations like getting input from keyboard, displaying information on screen and performing various other jobs.  These set of instructions are called 'machine language instructions '.  Processor understands only machine language instructions, which are strings of 1's and 0's.  But, machine language is too very complex for using in software development.  So, the assembly language is designed for a specific family of processors that represents various instructions in symbolic code and a more understandable form.

3. Objectives ASSEMBLY LANGUAGE PROGRAMMING 1. To develop an understanding of basic computer organization 2. To gain an understanding of the relationship between computer hardware and machine code/assembly code. 3. To develop skills in modular design and the implementation of software at the assembly level.

4. Other advantages of using assembly language are: It is a kind of Low level language Closer to M/C level and Hardware. For writing any high level language, It is mandatory to have knowledge of Assembly. While debugging a high level language program, we have to review the result in assembly language. Compiler writers must know how to write assembly language in order to have the code generation. It requires less memory and execution time; It allows hardware-specific complex jobs in an easier way; It is suitable for time-critical jobs; It is most suitable for writing interrupt service routines and other memory resident programs.Introduction

5. Basic Features of PC Hardware The main internal hardware of a PC consists of the processor, memory and the registers. The registers are processor components that hold data and address. To execute a program, the system copies it from the external device into the internal memory. The processor executes the program instructions.Introduction

6. Syllabus ASSEMBLY LANGUAGE PROGRAMMING SECTION-A Unit I: Deals with 8086 architecture, pin configuration, Memory address space and organization, memory address generation technique, Concept of Segment register. Unit II: About addressing modes, Instruction sets along with programming. Unit III : Logical Instruction, Flags Operations, Programming related to Loops. SECTION-B Unit IV : Stacks Subroutines, macros, Concept of recursion, Programming with subroutine and recursion.

7. Syllabus ASSEMBLY LANGUAGE PROGRAMMING Unit V: Study of 8255 Programmable Peripheral Interface, Types of I/P and O/P’s, different Modes and its operations. Unit VI: What is Interrupt, Types of interrupt, 8259 PIC Programmable Interrupt Controller modes and operation

8. Books ASSEMBLY LANGUAGE PROGRAMMING TEXT BOOKS: 1. W. A. Triebel & Avatar Singh: The 8088/8086 Microprocessors (4e) (PHI /Pearson Education) 2. Liu & Gibson: The 8088/8086 Microprocessor (2/e) (PHI) REFERENCES: 1. Barry B. Brey : The Intel Microprocessor Architecture, Programming & Interfacing (6/e)(PHI) 2. Ray & Bhurchandi: Advanced Microprocessors & Peripherals (TMH). 3. John P Uffenbeck, “8086/8088 Families: Designing, Programming and Interfacing”. Prentice Hall.

9. Introduction to CMOS VLSI Design Case Study: Intel Processors

10. Case Study: Intel Processors Outline Evolution of Intel Microprocessors ◦Scaling from 4004 to Pentium 4 ◦Courtesy of Intel Museum

11. Case Study: Intel Processors 4004 First microprocessor (1971) ◦For Busicom calculator Characteristics ◦10 m (micro meter) process ◦2300 transistors ◦400 – 800 kHz ◦4-bit word size ◦16-pin DIP package Masks hand cut from Rubylith ◦Drawn with color pencils ◦1 metal, 1 poly (jumpers) ◦Diagonal lines (!)

12. Case Study: Intel Processors 8008 8-bit follow-on (1972) Characteristics ◦10 m process ◦3500 transistors ◦500 – 800 kHz ◦8-bit word size ◦18-pin DIP package Note 8-bit datapaths ◦Individual transistors visible

13. Case Study: Intel Processors 8080 16-bit address bus (1974) ◦Used in Altair computer  (early hobbyist PC) Characteristics ◦6 m process ◦4500 transistors ◦2 MHz ◦8-bit word size ◦40-pin DIP package

14. Case Study: Intel Processors 8086 / 8088 16-bit processor (1978-9) ◦IBM PC and PC XT ◦Revolutionary products ◦Introduced x86 ISA Characteristics ◦3 m process ◦29k transistors ◦5-10 MHz ◦16-bit word size ◦40-pin DIP package Microcode ROM

15. Case Study: Intel Processors 80286 Virtual memory (1982) ◦IBM PC AT Characteristics ◦1.5 m process ◦134k transistors ◦6-12 MHz ◦16-bit word size ◦68-pin PGA Regular datapaths and ROMs Bitslices clearly visible

16. Case Study: Intel Processors 80386 32-bit processor (1985) ◦Modern x86 ISA Characteristics ◦1.5-1 m process ◦275k transistors ◦16-33 MHz ◦32-bit word size ◦100-pin PGA 32-bit datapath, microcode ROM, synthesized control

17. Case Study: Intel Processors 80486 Pipelining (1989) ◦Floating point unit ◦8 KB cache Characteristics ◦1-0.6 m process ◦1.2M transistors ◦25-100 MHz ◦32-bit word size ◦168-pin PGA Cache, Integer datapath, FPU, microcode, synthesized control

18. Case Study: Intel Processors Pentium Superscalar (1993) ◦2 instructions per cycle ◦Separate 8KB I$ & D$ Characteristics ◦0.8-0.35 m process ◦3.2M transistors ◦60-300 MHz ◦32-bit word size ◦296-pin PGA Caches, datapath, FPU, control

19. Case Study: Intel Processors Pentium Pro / II / III Dynamic execution (1995-9) ◦3 micro-ops / cycle ◦Out of order execution ◦16-32 KB I$ & D$ ◦Multimedia instructions ◦PIII adds 256+ KB L2$ Characteristics ◦0.6-0.18 m process ◦5.5M-28M transistors ◦166-1000 MHz ◦32-bit word size

20. Case Study: Intel Processors Pentium 4 Deep pipeline (2001) ◦Very fast clock ◦256-1024 KB L2$ Characteristics ◦180 – 90 nm process ◦42-125M transistors ◦1.4-3.4 GHz ◦32-bit word size ◦478-pin PGA Units start to become invisible on this scale

21. Case Study: Intel Processors Summary 10 4 increase in transistor count, clock frequency over 30 years!

22. The processor supports the following data sizes: Word: a 2-byte data item Doubleword: a 4-byte (32 bit) data item Quadword: an 8-byte (64 bit) data item Kilobyte: 1024 bytes Megabyte: 1024 K bytesIntroduction

23. The Binary Number System Every number system uses positional notation, i.e., each position in which a digit is written has a different positional value. Each position is power of the base, which is 2 for binary number system, and these powers begin at 0 and increase by 1. The following table shows the positional values for an 8-bit binary n Bit valueIntroduction Bit Value11111111 Position value as a power of base 2 1286432168421 Bit Number76543210

24. The value of a binary number is based on the presence of 1 bits and their positional value. So, the value of the given binary number is: 1 + 2 + 4 + 8 +16 + 32 + 64 + 128 = 255, which is same as 2 8 - 1.Introduction

25. The Hexadecimal Number System Hexadecimal number system uses base 16. The digits range from 0 to 15. By convention, the letters A through F is used to represent the hexadecimal digits corresponding to decimal values 10 through 15.Introduction DecimalBinaryHexadecimal 000 111 2102 3113 41004 51015 61106 71117 810008

26. Introduction DecimalBinaryHexadecimal 910019 101010A 111011B 121100C 131101D 141110E 151111F

27. Features of 8086  Intel 8086 was launched in 1978  It’s an first 16 bit Microprocessor  Having major improvement over the execution speed of 8085.  It is an 40 pin Dual-Inline-Package (DIP).  Available in three versions i. 8086 (5Mhz) ii. 8086 (8 Mhz) iii. 8086(10 Mhz)  It consist of 29000 transistors.  Microarchitecture of 8086 & 8088 are same, both implement parallel processing i.e. they consist of several simultaneously processing units.

28. Features of 8086 8086 has a 20 bit address bus can access upto 2 20 memory locations ( 1 MB). It can support upto 64K I/O ports. It consists fourteen(14), 16-bit registers. It has multiplexed address and data bus AD0- AD15 and A16 – A19 8086 is designed to operate in two modes, Minimum and Maximum. It can prefetches upto 6 instruction bytes from memory and queues them in order to speed up instruction execution. It requires +5V power supply. A 40 pin dual in line package.

29. Pipeline architecture of 8086 Execution Fetching Execution Unit Bus Interface Unit System Bus Fig : Pipeline architecture of 8086

30. Pipeline architecture of 8086 Microarchitecture of 8088/8086 Microprocessor Fig. Execution and Bus interface units of 8086 Microarchitectureq

31. Pipeline architecture of 8086  8086 has two blocks BIU and EU. 1. BIU : Bus Interface unit 2. 2. EU : Execution unit BIU : Provides connection to the outside world The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue. EU executes instructions from the instruction system byte queue.

32. Pipeline architecture of 8086  Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance. BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder. EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register, Flag register.

33. Pipeline architecture of 8086 Bus Interface Unit : It provides a full 16 bit bidirectional data bus and 20 bit address bus. The bus interface unit is responsible for performing all external bus operations. Specifically it has the following functions: Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control. The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture.

34. Pipeline architecture of 8086  This queue permits prefetch of up to six bytes of instruction code.  These prefetching instructions are held in its FIFO queue.  With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle.  The EU accesses the queue from the output end.  It reads one instruction byte after the other from the output of the queue. If the queue is full and the EU is not requesting access to operand in memory.  These intervals of no bus activity, which may occur between bus cycles are known as Idle state.

35. Pipeline architecture of 8086  The BIU also contains a dedicated adder which is used to generate the 20 bit physical address that is output on the address bus.  This address is formed by adding an appended 16 bit segment address and a 16 bit offset address. The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write.

36. Pipeline architecture of 8086 EXECUTION UNIT : The Execution unit is responsible for decoding and executing all instructions. The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write bys cycles to memory or I/O  Perform the operation specified by the instruction on the operands. During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction.

37. Pipeline architecture of 8086  If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue. When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions. Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue.  This is all about 8086 architecture.

38. Thank You