1. Computer Networks & Digital Lab project. In cooperation with Mellanox Technologies Ltd. Guided by: Crupnicoff Diego & Gurewitz Omer. Students: Cohen Erez, Gindi Nimrod & Krig Amit.

2. HW description. I2C connector FPGA Unit (125 MHz DDR) IB port 2.5 GB/sec (IB spec rev 1) SerDes 10  1 I2C interface transmitter

3. I2C Interface I2C software driver. 1 ) The first part is operating system level. Developing I2C driver for the I2C card on Linux platform. The I2C card (CALIBRE) ICA93LV/C Low-volt I2C Comms Adapter. as master on the I2C bus.

4. Device driver 2) Second part is the Device driver (FPGA driver). The API allows loading series of commands, Data array and a status registry. A 8bit to 10bit Library is mandatory. 8bit to 10bit translation is needed before loading the InfiniBand packet, in to the Data array.

5. I2C FPGA Interface The Command array. Transmit packet X Y1 times from port number 0 (the packet should already be in the data array). After transmitting Y1 times resume to the next command or to command number Z. The Data Array. X-entry array 32 bits each entry; you have an option to insert all kind of information to the data array. The Status registry. Points to the first command to start from.

6. Examples Data Array Status Register TS1 => address in the Board. TS2 => address in the Board. Idle Data => address in the Board. Flow Packet => address in the Board. Bad Packets => address in the Board. Command Array 1) Send TS1 2) Send TS2 3) Send Idle Data 4) Send Flow Packet 5) Send Bad Packet GO TO 3

7. FPGA Unit. The FPGA unit should have a FPGA Unit with I2C interface, as seen in the example above for the building blocks. (Command array, Data array and Status registry). The FPGA should transmit the 10bit in rate of 125MH DDR, which is 2.5 GB (Gig bit) per second. (InfiniBand 1X rate). The transmission should be at list (512 IB bytes), which means that a given X Bytes will be transmitted in one burst (no other data is allowed on the line between those Bytes). A transmission unit of 512 Bytes is necessary (in order to be able to generate SMP packets, which are 256 Bytes long).

8. FPGA Unit The FPGA unit should have the ability to transmit a given packet a specified number of times (or for a given time interval) from a given port. The API allows loading a command series of the type: Transmit packet X1 Y1 times from port P1. Wait T. (T >= 0) Transmit packet X2 Y2 times from port P1. After the command series are loaded to the memory, a command will be given to start the execution. For each link, when the link is idle, idle data shall be transmitted on the line. (To keep the Link up).

9. Physical Layer InfiniBand is a comprehensive architecture that defines both electrical and mechanical. characteristics for the system. These include cables and receptacles for fiber and copper. media; back plane connectors; and hot swap characteristics.

10. Sample Connector - Mechanical Characteristics

11. Physical Layer cont’ InfiniBand defines three link speeds at the physical layer, 1X, 4X, 12X. Each individual link is a four wire serial differential connection (two wires in each direction) that provide a full duplex connection at 2.5 Gb/s. These links are illustrated in Figure 6.

12. Physical Layer cont’