1. Output imageIntput image

2. Output imageIntput image

3. Address Calculator input output Coordinate(x,y) in output image 4 addresses (SDram) of input image

4. (x_start,y_start) Input imageOutput image

5. OutputSource (X,Y) R1 R2 Y’ X’ Y X

6. UART RX MessagePack Decoder MessagePack Decoder SDRAM Controller WBS WBM – Wishbone Master WBS – Wishbone Slave Mem Ctrl Wr Mem Ctrl Rd SDRAM Arbiter WBS MessagePack Encoder MessagePack Encoder UART TX WBM WBS WBM WBS WBM CheckSum RX Path TX Path Display Controller Display Controller Memory Management Memory Management WBS Wishbone INTERCON Wishbone INTERCON Pixel Manger Dual Clk FIFO VESA Ctrl. VESA Ctrl. - 133 MHz - 40 MHz Host (Matlab) VGA Display IS42S16400 SDRAM WBM Image Manipulation Addr Converter Biliniar Interpulation Addr Calculator Param Reg WBS

7. Flush UART RX MP Dec RAM 1 SDRAM Controller WBS WBM – Wishbone Master WBS – Wishbone Slave Mem Ctrl Wr Mem Ctrl Rd SDRAM Arbiter WBS RAM 2 MP Enc UART TX WBM WBS INTERCON FIFO VESA Ctrl. VESA Ctrl. req_ln_trig & Pixels, VSync Pixel Manager (Req for Data) Pixel Manager (Req for Data) WBM MUX Synthetic Pic. Gen Synthetic Pic. Gen WBS Flush Dual Clk FIFO WBM wr_rd_bank wr_cnt wr_cnt_en 8 bit Hsync, VSync CheckSum RX Path TX Path Display Controller Memory Management Memory Management WBS INTERCON TYPE Reg TYPE Reg Disp. Reg Frame Reg Frame Reg TYPE Reg DBG ADDR Reg DBG ADDR Reg INTERCON Rd Burst Len CRC ERR EOF ERR R1 R2 R1 – Ram 8  16 bits R2 – Ram 16  8 bits - 133 MHz - 40 MHz UART_SE UART_PE OR Host (Matlab) VGA Display IS42S16400 SDRAM DBG Command WBM Image Manipulation Addr Converter Biliniar Interpulation Addr Calculator Param Reg WBS