1. Status Presentation Group 7: 1394b Receiver Aparna Trimurty Stancil Starnes Jeff Shlipf March 28th, 2002.

2. Objective of presentation To report modifications and advancements to the project since the design report.To report modifications and advancements to the project since the design report. Status: stages 1 and 2 completed, stage 3 in progressStatus: stages 1 and 2 completed, stage 3 in progress

3. Stage 1 Purpose: testing an optomodule out of its original environment(TI card) by placing it on a evaluation board built by the group.Purpose: testing an optomodule out of its original environment(TI card) by placing it on a evaluation board built by the group. Opto module used: Agilent technologies HFBR-53D5Opto module used: Agilent technologies HFBR-53D5 Status : CompleteStatus : Complete

4. Stage 1: Design details

5. Stage 1: Test setup GTS 1250 GBIC test system pattern generatorGTS 1250 GBIC test system pattern generator Textronic TDS 7154 Digital Phosphor OscilloscopeTextronic TDS 7154 Digital Phosphor Oscilloscope

6. Stage 1: Test results Ch2 K28.7 Ch 2 PRBS7Ch 2 PRBS7

7. Stage 2 Purpose: testing the Maxim Receiver evaluation kitsPurpose: testing the Maxim Receiver evaluation kits MAX 3266 – transimpedance amplifier(TIA) MAX 3266 – transimpedance amplifier(TIA) MAX 3264 – limiting amplifier MAX 3264 – limiting amplifier Status: Complete.Status: Complete.

8. Stage 2: Design details MAX 3266 power connector design- can connect to a regular AC adaptor.MAX 3266 power connector design- can connect to a regular AC adaptor. MAX 3264- changed connectors of ac adaptor to match board connector.MAX 3264- changed connectors of ac adaptor to match board connector. Caused by a lack of accurate 5V power supplies.Caused by a lack of accurate 5V power supplies.

9. Stage 2: Testing

10. Stage 3 Purpose: the design and fabrication of a functional and cost effective receiver board based on the MAXIM boardPurpose: the design and fabrication of a functional and cost effective receiver board based on the MAXIM board Status: in progressStatus: in progress

11. Stage 3: modified design New designNew design Old designOld design

12. Stage 3: Modifications 1. The Level pin was grounded on the 3264 to maximize output voltage.1. The Level pin was grounded on the 3264 to maximize output voltage. 2. The Squelch pin was grounded on the 3264 to disable squelch. It is important to see all signals in testing, no matter how small they may be.2. The Squelch pin was grounded on the 3264 to disable squelch. It is important to see all signals in testing, no matter how small they may be. 3. The CAZ1 and CAZ2 pins on the 3264 are left open. In the specification sheet it is stated that for gigabit Ethernet these pins should be left open.3. The CAZ1 and CAZ2 pins on the 3264 are left open. In the specification sheet it is stated that for gigabit Ethernet these pins should be left open. 4. The Filter pin was left open on the 3266 to enable DC cancellation.4. The Filter pin was left open on the 3266 to enable DC cancellation. 5. The Loss-of-Signal circuit was omitted to further simplify the board. This also allowed for the TH pin to be left open as this simply sets the threshold of the LOS circuit.5. The Loss-of-Signal circuit was omitted to further simplify the board. This also allowed for the TH pin to be left open as this simply sets the threshold of the LOS circuit.

13. Stage 3: Modifications 6. The power filtering inductors were omitted. This was possible based on the fact that three separate supplies will be used and long power cords will be used between the board and the power supplied.6. The power filtering inductors were omitted. This was possible based on the fact that three separate supplies will be used and long power cords will be used between the board and the power supplied. 7. A single 1nF capacitor is used for decoupling the power supplies. Based on the use of three separate supplies 1nF should suffice.7. A single 1nF capacitor is used for decoupling the power supplies. Based on the use of three separate supplies 1nF should suffice. 8. Decoupling capacitors for the input and output of the circuit as well as between the TIA and LA chips were left in to maintain a good signal.8. Decoupling capacitors for the input and output of the circuit as well as between the TIA and LA chips were left in to maintain a good signal.

14. Stage 3: PCB layout and design considerations Red squares are power supplies. The input power is for the TIA, the 2 output ones are for LA ( as LA has 2 stages of amplification) 3 separate power supplies are used to reduce noise on board. Board layout assumes front pin of connector is ground and the inner pin is VCC. Power supplies not following this assumption will be modified to work with the design.

15. Proposed part list #Part DescriptionManufacturer Part Number Price (all) To Obtain 4.01uF capacitor – 0805 ECJ-2VB1H103K$.97Order from Digikey 31nF capacitor – 0805 ECU- V1H102MEN $.97Order from Digikey 1.1uF capacitor – 0805 ECJ-2VF1E104Z$1.06Order from Digikey 2100 Ohm resistors – 0805 ERJ-6GEYJ101V$.80Order from Digikey 167 Ohm resistor – 0805 ERJ-6GEYJ680V$.80Order from Digikey 150 Ohm resistor – 0805 ERJ-6ENF49R9V$.90Order from Digikey 3SWC Power Supply Connector RAPC722$3.12Edgar ordered some 3Jameco SMA connectors 901-143-6N/aA bag in lab

16. Future Considerations 1.Verifying the functionality of PCB board design. 2.Having Bob House create the board using the gerber file 3.Order part list. 4.Work on fixing the errors in our Agilent board that are ouputing an erroneous eye. 5.Solder, test, and troubleshoot the new board in a similar manner as the MAXIM kits. 6.If board produces a good eye it should be tested in conjunction with the 1394b transmitter board and OE board.