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TE/TM 30 th March - 0v1 CERN MPP SMP 3v0 - Introduction 3 *fast *safe *reliable *available generates flags & values.

Published byMyron Lynch Modified over 8 years ago

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Presentation on theme: "TE/TM 30 th March - 0v1 CERN MPP SMP 3v0 - Introduction 3 *fast *safe *reliable *available generates flags & values."— Presentation transcript:

1

2 SMP @ TE/TM 30 th March - 0v1

3 CERN bis-smp-team@cern.ch SMP @ MPP SMP 3v0 - Introduction 3 *fast *safe *reliable *available generates flags & values afe achine arameters SM P and / ordirectly transmittedbroadcast receives accelerator information injection procedureprotection configuration CERN = System Safety Beam Interlocks Collimation Beam Loss Monitors … Extraction Interlocks

4 CERN bis-smp-team@cern.ch SMP @ MPP Directly Transmitted

5 CERN bis-smp-team@cern.ch SMP @ MPP CERN bis-smp-team@cern.ch SMP @ MPP Extraction Interlocks 5 Transfer Lines Beam-1 = TT60 + TI2 Beam-2 = TT40 + TI8 Super Proton Synchrotron Large Hadron Collider Extraction Master Beam Interlock Controllers

6 CERN bis-smp-team@cern.ch SMP @ MPP Extraction Interlocks 6 Super Proton Synchrotron Large Hadron Collider

7 CERN bis-smp-team@cern.ch SMP @ MPP Extraction Interlocks 7 three beam transfer conditions: probe set-up nominal Super Proton Synchrotron Large Hadron Collider SPS Machine Parameters LHC Machine Parameters Directly Transmitted Interlock Signals

8 CERN bis-smp-team@cern.ch SMP @ MPP Broadcast

9 CERN bis-smp-team@cern.ch SMP @ MPP Protection Configuration 9 Super Proton Synchrotron Large Hadron Collider LHC Machine Parameters Broadcast Safe Machine Parameters SPS Machine Parameters

10 CERN bis-smp-team@cern.ch SMP @ MPP Controllers

11 CERN bis-smp-team@cern.ch SMP @ MPP Two Controllers 11

12 CERN bis-smp-team@cern.ch SMP @ MPP Dependable Electronics Basis

13 CERN bis-smp-team@cern.ch SMP @ MPP VME Chassis & Generic Circuit - CISX 13 Receiver – CISR Generator LHC – CISGL Generator SPS – CISGS Arbiter – CISA or

14 CERN bis-smp-team@cern.ch SMP @ MPP VME Chassis & Generic Circuit - CISX 14 Receiver – CISR Generator LHC – CISGL Generator SPS – CISGS Arbiter – CISA Monitor FPGA Control FPGA VHDL implementation Safety approach?

15 CERN bis-smp-team@cern.ch SMP @ MPP Hardware Dependable Design

16 CERN bis-smp-team@cern.ch SMP @ MPP Design flow

17 CERN bis-smp-team@cern.ch SMP @ MPP Requirements 17 Requirements requested by operators and/or approved by MPP. E.G. Set-up Beam Flag equation normal relaxed very relaxed ion

18 CERN bis-smp-team@cern.ch SMP @ MPP Specification and formalisation English + diagramspredicate logic vs English languageformal language Unlike the English, there is only one way to understand formal language.

19 CERN bis-smp-team@cern.ch SMP @ MPP Specification and formalisation English + diagramspredicate logic vs English languageformal language Unlike the English, there is only one way to understand formal language.

20 CERN bis-smp-team@cern.ch SMP @ MPP Functional blocks 20

21 CERN bis-smp-team@cern.ch SMP @ MPP Design flow

22 CERN bis-smp-team@cern.ch SMP @ MPP Implementation VHDL is not a programming language. It is a Hardware Description Language Must understand expected synthesis result comments and naming convention important for the code review Critical code = strict Non-Critical code = engineer has freedom High % code reuse

23 CERN bis-smp-team@cern.ch SMP @ MPP Design flow

24 CERN bis-smp-team@cern.ch SMP @ MPP Simulation Unit Under Test Bus Functional Model Register Transfer Level

25 CERN bis-smp-team@cern.ch SMP @ MPP Simulation Test-bench = software wrapped around model Simulation tool can examine code coverage response should be correct for all stimulus

26 CERN bis-smp-team@cern.ch SMP @ MPP Design flow

27 CERN bis-smp-team@cern.ch SMP @ MPP Hardware tester DeviceUnder Test

28 CERN bis-smp-team@cern.ch SMP @ MPP Hardware tester similar to simulation but real hardware embedded logic analyzers provided by FPGA vendors Chip Scope, SignalTap, … Hardware response should be correct for each stimulus

29 CERN bis-smp-team@cern.ch SMP @ MPP Hardware Dependable Design Summary Our approach – dependable PLD design goes on top of dependable electronics design exhaustive source code simulation full code coverage hardware testers formalisation of the specification split critical – non-critical reduction to minimum function code reviews external reviews

30 CERN bis-smp-team@cern.ch SMP @ MPP Software FESA – RBAC – MCS – Checks - GUI

31 CERN bis-smp-team@cern.ch SMP @ MPP Introduction 31 FESA class RBAC protection and MCS Operational checks SMP-GUI

32 CERN bis-smp-team@cern.ch SMP @ MPP FESA class 32 FESA class provides access to hardware registers no complex logic behind, just valid range checks Different type of access read-only access for everyone write access for experts trough dedicated expert properties write access for critical registers for operation

33 CERN bis-smp-team@cern.ch SMP @ MPP FESA class 33

34 CERN bis-smp-team@cern.ch SMP @ MPP RBAC and MCS configuration 34 SPS PropertyRolesApplicationsLocationMCS ProbeBeamLimitLHC-OP, LHC-EIC, MCS-SMPSEQUENCERX PropertyRolesApplicationsLocationMCS SqueezingFactorLHC-OP, LHC-EIC, MCS-SMPSISSIS-HOSTS SqueezingFactorLimitsLHC-OP, LHC-EIC, MCS-SMPSEQUENCERX PhysicsEnergyLimitsLHC-OP, LHC-EIC, MCS-SMPSEQUENCERX BeamModeLHC-OP, LHC-EIC, MCS-SMPSEQUENCER ForceSetupBeamFlagLHC-OP, LHC-EIC, MCS-SMPSMP-GUI SetupBeamFlagNormalLHC-OP, LHC-EIC, MCS-SMPSMP-GUI SetupBeamFlagSpecialSMP-THRESHOLD-EXPERTSMP-GUI ExpertRegisterSettingSMP-EXPERTSMP-GUI LHC

35 CERN bis-smp-team@cern.ch SMP @ MPP Operational checks 35 Pre-operational checks to ensure system ready for operation HW consistency vs DB, Test mode to ensure critical paths working to spec…

36 CERN bis-smp-team@cern.ch SMP @ MPP Operational checks 36 DIAMON checks to detect infrastructure issues PS, Timing, Communication problems…

37 CERN bis-smp-team@cern.ch SMP @ MPP Operational checks 37 Post-Mortem for post-operational check sequence Role played in last dump, Redundancy, Safety for next mission…

38 CERN bis-smp-team@cern.ch SMP @ MPP GUI Demonstration

39 CERN bis-smp-team@cern.ch SMP @ MPP SMP-GUI 39 GUI to monitor status of the systems (SPS and LHC) Send commands to the controllers Logged data viewer Useful tool for diagnostics Same tool used for Operators and Experts

40 CERN bis-smp-team@cern.ch SMP @ MPP Status & Future Plans

41 CERN bis-smp-team@cern.ch SMP @ MPP Q1/2 2011 41 + study intensity logic + ongoing documentation + 10 trivial issues in monitoring and diagnostics + beta Pre-Op + beta DIAMON + beta Post-Mortem

42 CERN bis-smp-team@cern.ch SMP @ MPP Q3/4 2011+ 42 + Cross-checker tester + Cross-checking hardware

43 CERN bis-smp-team@cern.ch SMP @ MPP Q3/4 2011+ 43

44 CERN bis-smp-team@cern.ch SMP @ MPP Q3/4 2011+ 44 + Cross-checker tester + Cross-checking hardware + VME Transmitter + VME Receiver

45 CERN bis-smp-team@cern.ch SMP @ MPP Q3/4 2011+ 45

46 CERN bis-smp-team@cern.ch SMP @ MPP Q3/4 2011+ 46

47 CERN bis-smp-team@cern.ch SMP @ MPP Q3/4 2011+ 47 + Cross-checker tester + Cross-checking hardware + VME Transmitter + VME Receiver + Pre-Op + DIAMON + Post-Mortem

48 CERN bis-smp-team@cern.ch SMP @ MPP In Closingfin – thank you!

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