1. The PHENIX Time Expansion Chamber A. Franz, J. Gannon, J. Mahon, S. Mioduszewski, E. O’Brien, R. Pisani, S. Rankowitz Brookhaven National Lab, Upton, New York Brookhaven National Lab, Upton, New York W.C. Chang Institute of Physics, Academia Sinica, Taiwan, Republic of China S. Bhaganatula, A. Lebedev, M. Rosati, T.Weimer S. Bhaganatula, A. Lebedev, M. Rosati, T.Weimer Iowa State University, Ames, Iowa Iowa State University, Ames, Iowa K. Barish, M. Bick, T. Ferdousi, S.Y. Fung, D. Kotchetkov, X.H. Li, M. Muniruzzaman, B. Nandi, R. Seto, W. Xie K. Barish, M. Bick, T. Ferdousi, S.Y. Fung, D. Kotchetkov, X.H. Li, M. Muniruzzaman, B. Nandi, R. Seto, W. Xie University of California-Riverside, Riverside, California University of California-Riverside, Riverside, California S. Botelho, O. Dietzsch, A. Lima deGodoi, E.M. Takagui S. Botelho, O. Dietzsch, A. Lima deGodoi, E.M. Takagui University of Sao Paulo, Sao Paulo, Brazil University of Sao Paulo, Sao Paulo, Brazil

2. The PHENIX Time Expansion Chamber 24 TEC chambers arranged in 4, 6 chamber sectors installed on East carriage Active area covers  /2 in azimuth,   0.35 Each 3.7 m x 2.0 m chamber contains 2700 wires (~900 anodes channels each) 2 sectors x 4 chambers instrum. RHIC2000 4 sectors x 4 chambers to be instrum. RHIC2001

3. The Time Expansion Chamber Performance Features: High p T Single point track resolution of 250 microns Large DC-TEC lever arm. Improves mom. resolution up to factor 5, p T > 4.0 GeV/c Particle ID e/π = 5% at 500 MeV/c using dE/dx (4 plnes) e/π =1. 5% at 500 MeV/c using dE/dx (6 plnes) Designed for TRD Upgrade. High mom. e/π Pattern Recognition Robust track reconstruction at high track densities

4. Time Expansion Chamber Electronics Up to 20,500 Instrumented TEC Channels 3 ASICs designed for TEC: –Octal Preamp/Shaper with tail cancellation and dual gain for both dE/dx and TRD. Full serial control of gain, shaping time and tail –Non-linear, 40 MHz, FADC with 9 bit dynamic range and precision with 5-bit encoding –Digital Memory Unit for data formatting and programmable delay and memory depth 32 channel Preamp/Shaper PCB with remote calibration control and ~ 1 fC RMS system noise Front End Module with digitizing, data formatting, and optical data transmission TEC PreampShaper PCB TECTEC Front End Module

5. TEC Performance Position Resolution (Test Beam) Pattern Recognition (RHIC ’00 Data) Momentum Reconstruction (Simulated) e/π Separation (Test Beam) PC3 TECToF

6. TEC Operation in RHIC 2000 Run dE/dx Energy loss in TEC planes clock tics counts TEC anode/cathode arrangement TEC signal timing

7. TEC Assembly Surveying completed chamber Wire divider Wires on anode/cathode boards Sector assembly with PC3 TEC installed on East Carriage Epoxying the wires on the TEC

8. TEC Track Reconstruction with B-field TEC Tracking Data with Increasing Centrality dNc/dy  150 dNc/dy  300dNc/dy  500

9. TEC Data from RHIC ‘00 Run TEC Track Multiplicity South vs North Sectors ToF Clusters vs TEC Reconstructed Tracks Conclusion: PHENIX TEC Works Well. Calibration & Data Analysis is Underway TEC Tracks ToF Clusters TEC Tracks N TEC Tracks S