1. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg1 STEREO IMPACT POWER SUPPLIES Peter Berg, UC Berkeley Space Sciences Lab, pcb@ssl.berkeley.edu, (510) 643-9443 pcb@ssl.berkeley.edu

2. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg2 SPECIFICATION EXTRACT

3. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg3 CONTROLLING DOCUMENTS STEREO EMC Control Plan and EMI PerformanceRequirements Specification, 7381-9030 IMPACT/PLASTIC Power Converter Requirements Performance Assurance Implementation Plan

4. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg4 MASS AND POWER ESTIMATES

5. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg5 STEREO IMPACT HVPS (SIT)

6. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg6 STEREO SIT HVPS ETU

7. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg7 HVPS MULTIPLIER STACK

8. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg8 SIT HVPS ETU TEST DATA

9. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg9 HIGH VOLTAGE MANUFACTURING FLOW VISUALLY INSPECT AND ALCOHOL CLEAN PWB BAKE BOARD OVERNIGHT @ 60C LOAD SURFACE MOUNT LOW VOLTAGE PARTS INSTALL DRIVE TRANSISTORS, HEAT SINK AND BRACKET INSTALL SHIELDING WALLS LOAD THROUGH HOLE PARTS IN LOW VOLTAGE SECTION EXCEPT OUTPUT TRANSISTORS INSTALL STANDOFFS INSTALL FEEDBACK RESISTOR EPOXY WALLS TO BOX- BAKE 2HR @ 65C QA

10. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg10 HIGH VOLTAGE MANUFACTURING FLOW BEND HV DIVIDER RESISTORS SILVER EPOXY DIVIDER RESISTORS – BAKE 1HR @100C ELECTRICAL TEST SEAL GAPS TO PREPARE FOR POTTING STAKE CLEAN AND DRY OVERNIGHT ALCOHOL LEAK CHECK, THEN 1HR BAKE @ 50C VACUUM BAKE OVERNIGHT @82C TO OUTGAS EPOXY MULTIPLIER TO BOARD – BAKE 2HR @ 65C SILVER EPOXY OUTPUT FILTER CAPACITORS TO BOARD – BAKE 1 HR @ 100C INSTALL OUTPUT CABLES AND STAKE INSTALL TRANSFORMER QA

11. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg11 HIGH VOLTAGE MANUFACTURING FLOW GLUE STACK PRESSURE DISPERSER TIE DOWN AND WEDGE COMPRESSION FIBER EPOXY KNOTS, CURE 2HR@ 60C ELECTRICAL TEST VACUUM POT @60C POUR OUT POTTING AT NORMAL AIR PRESSURE, SIT FOR 4 DAYS STORE IN 55C OVEN WHILE MIXING POTTING CLEAN, REMOVE SEALING/MASKING STAKING COAT BOTTOM, SIT OVERNIGHT, THEN BAKE 24HRS @60C QA

12. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg12 LOW VOLTAGE FLIGHT MANUFACTURING FLOW VISUALLY INSPECT AND ALCOHOL CLEAN PWB BAKE BOARD OVERNIGHT @ 60C LOAD SURFACE MOUNT PARTS INSTALL IN BOX CLEAN LOAD THROUGH HOLE PARTS ELECTRICAL TEST STAKE & CURE COAT & CURE QA ELECTRICAL TEST TORQUE QA CLEAN

13. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg13 INTERFACES 6 SWEA 2.5V Bias Voltage -5.1VA +5.1VA +28V return 1,8 +28V 6 +5.1VA Airborn M83513/04-C11N 5 17 16 7 14 8 6 13 20 15 10 9 18 19 21 11 4 1 2 3 12 6 +5VD VCC_A -12.1VA Bias Return -12.1VA 6 -5.1VA +12.1VA SIT HVPS IDPU Digital Ground ANALOG GROUND +28V(secondary)

14. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg14 SEP 49 SIT +6A 42 CENTRAL +5.1D 18 SIT +5A RTN 18 BIAS RTN 50 SIT +5A RTN 43 BIAS RTN 19 SIT -6A 19 LVPS TEMP SENSOR 51 SIT -6A 44 +28V OP HTR 20 SIT -13A 20 +28V OP HTR 52 SIT -13A 45 +28V OP HTR RTN 21 SIT -5.2D 21 +28V OP HTR RTN 53 SIT -5.2D 46 +28V SURV HTR 22 SIT +2.6D 22 +28V SURV HTR 54 SIT +2.6D 47 +28V SURV HTR RTN 23 SIT +3.4D 23 +28V SURV HTR RTN 55 SIT +3.4D 48 Spare 24 SIT +5.1D 24 Spare 56 SIT +5.1D 49 Spare 25 HET PWR RTN 25 Spare 57 HET PWR RTN 50 Spare 26 HET +13A 51 Spare 58 HET +13A 27 HET +6A 59 HET +6A 28 HET -6A 60 HET -6A 29 HET -13A 61 HET -13A 30 HET +2.6D 62 HET +2.6D 31 HET +3.4D 63 HET +3.4D 32 HET +5.1D 64 HET +5.1D 65 Spare SEP J12 A, LVPS OUTPUT J1, SEP INPUT J12 B, LVPS OUTPUT 1 SEPT-NS ANA RTN1 Spare1 LET PWR RTN 33 SEPT-NS ANA RTN2 +28V MAIN/OP HTR26 LET PWR RTN 2 SEPT-NS +5.6A3 +28V MAIN/OP HTR2 LET +13A 34 SEPT-NS +5.6A4 Spare27 LET +13A 3 Spare5 +28V SURV HTR3 LET +6A 35 Spare6 +28V SURV HTR28 LET +6A 4 SEPT-NS DIG RTN7 Spare4 LET -6A 36 SEPT-NS DIG RTN8 CHASSIS29 LET -6A 5 SEPT-NS +2.6D9 Spare5 LET -13A 37 SEPT-NS +2.6D10 +28V MAIN/OP HTR RTN30 LET -13A 6 SEPT-NS +5.3D11 +28V MAIN/OP HTR RTN6 LET +2.6D 38 SEPT-NS +5.3D12 Spare31 LET +2.6D 7 SEPT-NS SEP STAR13 +28V SURV HTR RTN7 LET +3.4D 39 SEPT-NS SEP STAR14 +28V SURV HTR RTN32 LET +3.4D 8 SEPT-E ANA RTN15 PWR HRNS SHLD8 LET +5.1D 40 SEPT-E ANA RTN 33 LET +5.1D 9 SEPT-E +5.6A 9 CENTRAL ANA RTN 41 SEPT-E +5.6A 34 CENTRAL ANA RTN 10 Spare 10 CENTRAL +13A 42 Spare 35 CENTRAL +13A 11 SEPT-E DIG RTN 11 CENTRAL +6A 43 SEPT-E DIG RTN 36 CENTRAL +6A 12 SEPT-E +2.6D 12 CENTRAL -6A 44 SEPT-E +2.6D 37 CENTRAL -6A 13 SEPT-E +5.3D 13 CENTRAL -13A 45 SEPT-E +5.3D 38 CENTRAL -13A 14 SEPT-E SEP STAR 14 CENTRAL DIG RTN 46 SEPT-E SEP STAR 39 CENTRAL DIG RTN 15 SIT PWR RTN 15 CENTRAL +2.6D 47 SIT PWR RTN 40 CENTRAL +2.6D 16 SIT +13A 16 CENTRAL +3.4D 48 SIT +13A 41 CENTRAL +3.4D 17 SIT +6A 17 CENTRAL +5.1D

15. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg15 IDPU LVPS BLOCK DIAGRAM INPUT FILTER SOFT START BUCK DOWN CONVERSION 300 KHZ OSCILLATOR +5V SUPPLY, PWM TOPOLOGY LDO LDO TOPOLOGY + 12 Volts Internal +5 Volts Internal 300 KHz, Internal +12 Volts Internal S/C 28 BUCK DOWN CONVERSION 2.5V 5V ±12.8V SUPPLY,CURRENT FED TOPOLOGY +5 Volts Regulated -12.8V -5V Analog +12.8V +5V Analog 100V SUPPLY,RESONANT TOPOLOGY Sync +0 to 100V 300 KHz, Internal +12 Volts Internal +5 Volts Internal

16. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg16 SEP LVPS BLOCK DIAGRAM INPUT FILTER SOFT START BUCK DOWN CONVERSION 300 KHZ OSCILLATOR ± 13V, ± 6VA SUPPLY, PWM TOPOLOGY + 12 Volts Internal +5 Volts Internal 300 KHz, Internal +12 Volts Internal S/C 28 2.5V BUCK DOWN CONVERSION 2.6 V 3.3V 5.1 V ±5.1 V -5.2, +5VD 300 KHz, Internal ± 13 V ± 6VA +5 Volts Internal LDO -5.2, +5 SUPPLY, PWM TOPOLOGY 3.3V BUCK DOWN CONVERSION ± 5.1,SUPPLY, PWM TOPOLOGY +5.1 SUPPLY, PWM TOPOLOGY +2.6V BUCK DOWN CONVERSION 2.5 THIS SECTION IS REPEATED, SEPT NS AND SEPT E

17. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg17 SWEA LVPS BLOCK DIAGRAM INPUT FILTER SOFT START BUCK DOWN CONVERSION 300 KHZ OSCILLATOR +5V SUPPLY, PWM TOPOLOGY LDO + 12 Volts Internal +5 Volts Internal 300 KHz, Internal +12 Volts Internal S/C 28 BUCK DOWN CONVERSION 2.5V 5V ±12V, ± 5V SUPPLY, PWM TOPOLOGY -12V -5V +12V +5V 140V SUPPLY,RESONANT TOPOLOGY Sync +0 to 140V 300 KHz, Internal +12 Volts Internal +5 Volts Internal +28V SUPPLY, PWM TOPOLOGY +5 Volts Internal 28V 300 KHz, Internal +12 Volts Internal +5 Volts Internal

18. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg18 PLASTIC LVPS BLOCK DIAGRAM INPUT FILTER SOFT START BUCK DOWN CONVERSION 300 KHZ OSCILLATOR ± 5V, ±12V SUPPLY, PWM TOPOLOGY LDO + 12 Volts Internal +5 Volts Internal 300 KHz, Internal +12 Volts Internal S/C 28 BUCK DOWN CONVERSION 2.5V 5V +12.8V 300 KHz, Internal +5 Volts Internal

19. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg19 HIGH VOLTAGE MANUFACTURING FLOW VISUALLY INSPECT AND ALCOHOL CLEAN PWB BAKE BOARD OVERNIGHT @ 60C LOAD SURFACE MOUNT LOW VOLTAGE PARTS INSTALL DRIVE TRANSISTORS, HEAT SINK AND BRACKET INSTALL SHIELDING WALLS LOAD THROUGH HOLE PARTS IN LOW VOLTAGE SECTION EXCEPT OUTPUT TRANSISTORS INSTALL STANDOFFS INSTALL FEEDBACK RESISTOR EPOXY WALLS TO BOX- BAKE 2HR @ 65C QA

20. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg20 SCHEMATICS

21. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg21

22. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg22 IDPU

23. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg23 SEP

24. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg24 SWEA

25. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg25 PLASTIC

26. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg26 IDPU LVPS

27. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg27 SWEA

28. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg28 PLASTIC

29. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg29 SEP LVPS

30. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg30 STATUS SIT HV ETU BUILT AND DELIVERED IDPU LVPS BOX FABRICATED, ETU IN TEST SCHEMATICS MOSTLY COMPLETE

31. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg31 PEER REVIEW RFAs IMPACT UCB LVPS/HVPS Review CLOSURE STATUS (8/9/02) Action No. Action Item TITLE ORIGINATOR STATUS DATE CLOSED 1HVPS Temperature testBrian King 2SIT HVPS GroundingShane Hynes 3Potting materialHarry Culver 4Capacitive load testingHarry Culver 5LVPS Soft StartShane Hynes 6LVPS Input Voltage TestingHarry Culver 7Oscillation ProtectionHarry Culver 8Loss of synchronization circuitryHarry Culver 9Survival of 40VHarry Culver 10IDPU LVPS ClarityHarry Culver 11Add grounding jumpersHarry Culver 12Terminate shieldsHarry Culver 13Add capacitorHarry Culver 14PLASTIC ripple requirementsShane Hynes 15Grounding requirement for PLASTIC LVPSKen Crocker TBDone Submitted Done Designed Done Designed Done Received Submitted RESPONSE

32. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg32 WHATS LEFT SIT HV ETU – RESOLVE ETU TEST ISSUES IDPU FINISH ETU TEST SIT, SEPT, PLASTIC –> LAYOUT, BUILD AND TEST ETUS

33. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg33 VERIFICATION PERFORM CE TESTS ON FINISHED ETUS

34. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg34 ETU DELIVERY SCHEDULE IDPU DEC 30, 2002 SEP JAN 30, 2003 SWEA, FEB 28, 2003 PLASTIC MAR 15, 2003

35. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg35

36. STEREO IMPACT Critical Design Review 2002 November 20,21,22 P.Berg36 KNOWN ISSUES SIT HVPS RESOLVE CONSUMPTION VS SYNC RESOLVE SPECIFICATIONS SCHEDULE PARTS ISSUES LONG LEAD TIMES ON HV MOX RESISTORS LTC1877 PWM METALIZATION REVISE PRIORITIES, ADD MANPOWER