1. 1 Virtual Memory

2. 2 Outline Virtual Space Address translation Accelerating translation –with a TLB –Multilevel page tables Different points of view Suggested reading: 10.1~10.6 TLB: Translation lookaside buffers

3. 3 10.1 Physical and Virtual Addressing

4. 4 Physical Addressing Attributes of the main memory –Organized as an array of M contiguous byte-sized cells –Each byte has a unique physical address (PA) started from 0 physical addressing –A CPU use physical addresses to access memory Examples –Early PCs, DSP, embedded microcontrollers, and Cray supercomputers Contiguous: 临近的

5. 5 Physical Addressing Figure 10.1 P693

6. 6 Virtual Addressing Virtual addressing –the CPU accesses main memory by a virtual address (VA) The virtual address is converted to the appropriate physical address

7. 7 Virtual Addressing Address translation –Converting a virtual address to a physical one –requires close cooperation between the CPU hardware and the operating system the memory management unit (MMU) –Dedicated hardware on the CPU chip to translate virtual addresses on the fly A look-up table –Stored in main memory –Contents are managed by the operating system

8. 8 Figure 10.2 P694

9. 9 10.2 Address Space

10. 10 Address Space –An ordered set of nonnegative integer addresses Linear Space –The integers in the address space are consecutive N-bit address space

11. 11 Address Space K=2 10 (Kilo), M=2 20 (Mega), G=2 30 (Giga), T=2 40 (Tera), P=2 50 (Peta), E=2 60 (Exa) #virtual address bits (n) #virtual address (N) Largest possible virtual address 8 64K 32 256T 64 256 255 1664K-1 4G4G-1 48 16E16E-1 256T-1 Practice Problem 10.1 P695

12. 12 Address Space Data objects and their attributes –Bytes vs. addresses Each data object can have multiple independent addresses

13. 13 10.3 VM as a Tool for Caching

14. 14 Using Main Memory as a Cache P695 DRAM SRAM Disk

15. 15 10.3.1 DRAM Cache Organization

16. 16 Using Main Memory as a Cache DRAM vs. disk is more extreme than SRAM vs. DRAM –Access latencies: DRAM ~10X slower than SRAM Disk ~100,000X slower than DRAM –Bottom line: Design decisions made for DRAM caches driven by enormous cost of misses

17. 17 Design Considerations Line size? –Large, since disk better at transferring large blocks Associativity? –High, to minimize miss rate Write through or write back? –Write back, since can’t afford to perform small writes to disk

18. 18 10.3.2 Page Tables

19. 19 Page Virtual memory –Organized as an array of contiguous byte-sized cells stored on disk conceptually. –Each byte has a unique virtual address that serves as an index into the array –The contents of the array on disk are cached in main memory

20. 20 Page P695 The data on disk is partitioned into blocks –Serve as the transfer units between the disk and the main memory –virtual pages (VPs) –physical pages (PPs) Also referred to as page frames

21. 21 Page Attributes P695 1) Unallocated: –Pages that have not yet been allocated (or created) by the VM system –Do not have any data associated with them –Do not occupy any space on disk.

22. 22 Page Attributes 2) Cached: –Allocated pages that are currently cached in physical memory. 3) Uncached: –Allocated pages that are not cached in physical memory.

23. 23 Page Figure 10.3 P696

24. 24 Page Table Each allocate page of virtual memory has entry in page table Mapping from virtual pages to physical pages –From uncached form to cached form Page table entry even if page not in memory –Specifies disk address OS retrieves information

25. 25 Page Table Data 243 17 105 0: 1: N-1: X Object Name Location D: J: X:1 0 On Disk “Cache”Page Table

26. 26 Page Table Memory resident page table (physical page or disk address) Physical Memory Disk Storage (swap file or regular file system file) Valid 1 1 1 1 1 1 1 0 0 0 Virtual Page Number

27. 27 10.3.3 Page Hits

28. 28 Page Hits Figure 10.5 P698 Memory Address Translation: Hardware converts virtual addresses to physical addresses via an OS-managed lookup table (page table) CPU 0: 1: N-1: 0: 1: P-1: Page Table Disk Virtual Addresses Physical Addresses

29. 29 10.3.4 Page Faults

30. 30 Page Faults Page table entry indicates virtual address not in memory OS exception handler invoked to move data from disk into memory –current process suspends, others can resume –OS has full control over placement, etc. Suspend: 悬挂

31. 31 Page Faults Swapping or paging Swapped out or paged out (from DRAM to Disk) Demand paging (Waiting until the last moment to swap in a page, when a miss occurs) CPU Memory Page Table Disk Virtual Addresses Physical Addresses CPU Memory Page Table Disk Virtual Addresses Physical Addresses Before fault After fault Figure 10.6 P699Figure 10.7 P699

32. 32 Servicing a Page Fault Processor Signals Controller –Read block of length P starting at disk address X and store starting at memory address Y disk Disk disk Disk Memory-I/O bus Processor Cache Memory I/O controller I/O controller Reg (1) Initiate Block Read

33. 33 Servicing a Page Fault Read Occurs –Direct Memory Access (DMA) –Under control of I/O controller disk Disk disk Disk Memory-I/O bus Processor Cache Memory I/O controller I/O controller Reg (2) DMA Transfer

34. 34 Servicing a Page Fault I / O Controller Signals Completion –Interrupt processor –OS resumes suspended process disk Disk disk Disk Memory-I/O bus Processor Cache Memory I/O controller I/O controller Reg (3) Read Done Resumes: 再继续, 重新开始

35. 35 10.3.5 Allocating Pages

36. 36 Allocating Pages P700 The operating system allocates a new page of virtual memory, for example, as a result of calling malloc. Figure 10.8 P700

37. 37 10.3.6 Locality to the Rescue Again Rescue: 解救

38. 38 Locality P700 The principle of locality promises that at any point in time they will tend to work on a smaller set of active pages, known as working set or resident set. Initial overhead where the working set is paged into memory, subsequent references to the working set result in hits, with no additional disk traffic.

39. 39 Locality-2 P700 If the working set size exceeds the size of physical memory, then the program can produce an unfortunate situation known as thrashing, where the pages are swapped in and out continuously. Thrash: 鞭打

40. 40 10.4 VM as a Tool for Memory Management

41. 41 A Tool for Memory Management Separate virtual address space –Each process has its own virtual address space Simplify linking, sharing, loading, and memory allocation

42. 42 10.4.1 Simplifying Linking

43. 43 A Tool for Memory Management Virtual Address Space for Process 1: Physical Address Space (DRAM) VP 1 VP 2 PP 2 Address Translation 0 0 N-1 0 M-1 VP 1 VP 2 PP 7 PP 10 (e.g., read/only library code)... Virtual Address Space for Process 2: Figure 10.9 P701

44. 44 A Tool for Memory Management kernel virtual memory Memory mapped region for shared libraries runtime heap (via malloc) program text (.text) initialized data (.data) uninitialized data (.bss) stack forbidden %esp memory invisible to user code the “brk” ptr Linux/x86 process memory image Figure 10.10 P702 0xc0000000 0xbfffffff 0x40000000 0x08048000

45. 45 10.4.2 Simplifying Sharing

46. 46 Simplifying Sharing In some instances, it is desirable for processes to share code and data. –The same operating system kernel code –Make calls to routines in the standard C library The operating system can arrange for multiple process to share a single copy of this code by mapping the appropriate virtual pages in different processes to the same physical pages

47. 47 10.4.3 Simplifying Memory Allocation

48. 48 Simplifying Memory Allocation A simple mechanism for allocating additional memory to user processes. Page table work.

49. 49 10.4.4 Simplifying Loading

50. 50 Simplifying Loading Load executable and shared object files into memory. Memory mapping……mmap

51. 51 10.5 VM as a Tool for Memory Protection

52. 52 A Tool for Memory Protection Page table entry contains access rights information –hardware enforces this protection (trap into OS if violation occurs)

53. 53 A Tool for Memory Protection Page Tables Process i: Physical AddrRead?Write? PP 9YesNo PP 4Yes XXXXXXX No VP 0: VP 1: VP 2: Process j: 0: 1: N-1: Memory Physical AddrRead?Write? PP 6Yes PP 9YesNo XXXXXXX No VP 0: VP 1: VP 2:

54. 54 A Tool for Memory Protection Figure 10.11 P704

55. 55 10.6 Address Translation

56. 56 Address Translation Processor Hardware Addr Trans Mechanism fault handler Main Memory Secondary memory a a'  page fault physical address OS performs this transfer (only if miss) virtual addresspart of the on-chip memory mgmt unit (MMU)

57. 57 Address Translation Figure 10.12 P705 Parameters –P = 2 p = page size (bytes). –N = 2 n = Virtual address limit –M = 2 m = Physical address limit

58. 58 Address Translation P705 virtual page numberpage offset virtual address physical page numberpage offset physical address 0p–1 address translation pm–1 n–10p–1p Notice that the page offset bits don't change as a result of translation

59. 59 Address Translation via Page Table virtual page number (VPN)page offset virtual address physical page number (PPN)page offset physical address 0p–1pm–1 n–10p–1p page table base register (PTBR) if valid=0 then page not in memory valid physical page number (PPN) access VPN acts as table index Figure 10.13 P705

60. 60 10.6.4 Putting it Together: End-to-End Address Translation

61. 61 Simple Memory System Example Addressing –14-bit virtual addresses –12-bit physical address –Page size = 64 bits 131211109876543210 11109876543210 VPO PPOPPN VPN (Virtual Page Number) (Virtual Page Offset) (Physical Page Number) (Physical Page Offset) Figure 10.20 P712

62. 62 Simple Memory System Page Table Only show first 16 entries VPNPPNValidVPNPPNValid 0028108131 01–009171 023310A091 030210B–0 04–00C–0 051610D2D1 06–00E111 07–00F0D1 Figure 10.21 P712 (b)

63. 63 Address Translation Example P714 Virtual Address 0x03D4 131211109876543210 VPO VPN 00101011110000 VPN: 0x0f Page Fault? No PPN: 0x0D VPO: 0x14 PA: 0x354 11109876543210 PPOPPN 001010101100

64. 64 Page Hits Figure 10.14 (a) P706 VA: virtual address. PTEA: page table entry address. PTE: page table entry. PA: physical address.

65. 65 Page Faults Figure 10.14 (b) P706

66. 66 10.6.1 Integrating Caches and VM

67. 67 Integrating Caches and VM CPU Trans- lation Cache Main Memory VAPA miss hit data

68. 68 Integrating Caches and VM Most Caches “Physically Addressed” –Accessed by physical addresses –Allows multiple processes to have blocks in cache at same time –Allows multiple processes to share pages –Cache doesn’t need to be concerned with protection issues Access rights checked as part of address translation

69. 69 Integrating Caches and VM Perform Address Translation Before Cache Lookup –But this could involve a memory access itself (of the PTE) –Of course, page table entries can also become cached

70. 70 Figure 10.15 P708

71. 71 10.6.2 Speeding up Address Translation with a TLB

72. 72 Speeding up Translation with a TLB “Translation Lookaside Buffer” (TLB) –Small hardware cache in MMU –Maps virtual page numbers to physical page numbers

73. 73 Figure 10.17 (a) P709

74. 74 Speeding up Translation with a TLB Figure 10.16 P708

75. 75 Speeding up Translation with a TLB virtual address virtual page number page offset physical address n–10p–1p validphysical page numbertag validtagdata = cache hit tagbyte offset index = TLB hit TLB Cache...

76. 76 TLB –16 entries –4-way associative 131211109876543210 VPO VPN TLBI TLBT SetTagPPNValidTagPPNValidTagPPNValidTagPPNValid 003–0090D100–007021 1032D102–004–00A–0 202–008–006–003–0 307–0030D10A34102–0 Simple Memory System TLB Figure 10.21 (a) P712

77. 77 Address Translation Example P714 Virtual Address 0x03D4 131211109876543210 VPO VPN 00101011110000 VPN: 0x0f TLBI: 0x03 TLBT: 0x03 TLB Hit? yes Page Fault? No PPN: 0x0D VPO: 0x14 PA: 0x354 11109876543210 PPOPPN 001010101100

78. 78 Simple Memory System Cache Cache –16 lines –4-byte line size –Direct mapped

79. 79 Simple Memory System Cache 11109876543210 PPOPPN CO CI CT IdxTagValidB0B1B2B3IdxTagValidB0B1B2B3 01919911231182413A005189 1150––––92D0–––– 21B100020408A2D19315DA3B 3360––––B0B0–––– 4321436D8F09C120–––– 50D13672F01DD16104963415 6310––––E13183771BD3 716111C2DF03F140–––– Figure 10.21 (c) P713

80. 80 Address Translation Example P714 PA: 0x354 11109876543210 PPOPPN CO CI CT 001010101100 Offset: 0x0 CI: 0x05 CT: 0x0D Hit? Yes Byte: 0x36

81. 81 10.6.3 Multi Level Page Tables

82. 82 Multi-Level Page Tables Given: –4KB (2 12 ) page size –32-bit address space –4-byte PTE Problem: –Would need a 4 MB page table! 2 20 *4 bytes

83. 83 Multi-Level Page Tables Common solution –multi-level page tables –e.g., 2-level table (P6) Level 1 table: 1024 entries, each of which points to a Level 2 page table. Level 2 table: 1024 entries, each of which points to a page Level 1 Table... Level 2 Tables

84. 84 Multi-Level Page Tables Figure 10.18 P710

85. 85 Multi-Level Page Tables Figure 10.19 P711