1. DDR1 using AMBA Design ware Memory Controller interfacing with MICRON 16VDDF12864HY We use DDR1 and testing the design using Virtex-5 FPGA. HCLK(DDR CLK) = 75MHz, MCLK(2xHCLK) = 150MHz, 16-bit Interface. All the Timing control register, latency(2) are changed to run at 75MHz and controller is re initialized at the end before read/write is attempted. Slide-3 (block diagram) – Signals highlighted are probed using Xilinx chip scope at respective points. – Few control signals are tapped before interface module, due to routing complexities, so all the probed signals are not 100% cycle matched on waveform, so the description of interface module is attached in slide3 for reference,(for ex RAS,CAS.. are tapped before DDR interface module and WR_DQS is tapped after the interface before moving to IO). Slide-4(Read/Write), Slide-5(Write Zoomed), Slide-6(Read Zoomed) Slide-7(Configuration after the 200us wait triggered when CKE goes high) Issue – We do not see the memory responding back to the controller.

2. AMBA MCTL IFC DDR interface (write pipe adjustments). REFER NEXT SLIDE For More info MIC RON DDR 1 Me mor y MT1 6VD DF1 286 4HY.. WR_DQS[1:0] DDR_WR_DATA[15:0] DDR_RD_LDATA[15:0] DDR_RD_UDATA[15:0] RD_DQS[1:0] IO BUF IO BUF DDR_DOUT_VALID[1:0] IDDR DDR_CLK_O_SIG CLK_MCTL (DDR_CLK_O_SIG * 2) DDR_CK DDR_CK_n MCTL_RAS_n MCTL_CAS_n MCTL_WE_n MCTL_SEL_n MCTL_DOUT_VALID MCTL_CKE DQS_IO DQ_IO

3. DDR interface Write Pipe //-------------------------------------------------------- // 1 Write Pipe //------------------------------------------------------ always @(posedge clk) begin ddr_addr <= mctl_addr; ddr_bank_addr <= mctl_bank_addr; ddr_sel_n <= mctl_sel_n; ddr_ras_n <= mctl_ras_n; ddr_cas_n <= mctl_cas_n; ddr_cke <= mctl_cke; ddr_we_n <= mctl_we_n; ddr_dout_valid<= mctl_dout_valid; end always @(negedge clk_2x) begin dqm_tmp <= dqm; ddr_dqm <= dqm_tmp; wr_data_tmp <= wr_data; ddr_wr_data <= wr_data_tmp; end always @(posedge clk_2x) begin dqs_tmp <= dqs; ddr_wr_dqs <= dqs_tmp; end

4. Write followed by Read Snapshot

5. Write Zoomed

6. Read Zoomed

7. Initialization