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4 Marketing Requirements Engineering RequirementsJustification 10 A. User interface will consist of a single on/off switch. The system does not need to be configured by the user. 6 B. The design process will be well-documented. Documentation is important for any future work that may be done on the project. It can also be used as a resource for other projects. 4,10 C. Upon power up, the system will counteract noise signals which fall between 420 Hz and 460 Hz. This chosen frequency range signifies all the unwanted noise the system will need to counter- act. This range does not need to be configured by the user. 5,6 D. The output of the system will be a 3.5 mm headphones jack. The 3.5 mm headphone jack is the standard for many electronic devices. 3 E. The cost of the system will not exceed $1000 per academic unit. Keeping the cost of the system to $1000 per unit will help make the system more affordable and marketable to customers. 1,2,7,8,11 F. The processor and all internal connections must be encompassed in a hard case with dimensions no more than four inches larger than the dimensions of the FPGA. Keeping the system enclosed in a case that is about the size of the board used will ensure that the system is safe, small, easy to move, durable, and more aesthetically pleasing to the customer.

5 Marketing RequirementsEngineering RequirementsJustification 5,8 G. The system must contain two microphones, an FPGA, necessary wires, a headset, and a hard case. The basic components are what the system needs to work. 4 H. The microphones must be able to detect frequencies in the range 60 Hz to 15 kHz. This is a basic need of the system so that it can detect the noise signals which must be countered. 3,9,12 I. The system must consume less than 0.3 kWh on average. With a low power consumption, the product is more affordable. Low-power systems also do not produce much heat. 1,12 J. The system must not exceed a peak instantaneous power usage of 10 W. Putting a cap on the peak power usage of the system will act as a safety feature to keep it from tripping breakers or drawing more than a desired amount of power at any given point in time. This will also ensure that the system stays energy efficient. 4 K. A drop in the volume of the noise signal must be detected by 85% of individuals who test the system. The noise signal will not be completely countered; however, a drop in volume should be able to be detected by a customer with average hearing capabilities.

6 Marketing RequirementsEngineering RequirementsJustification 4,14 L. The delay between the point at which the system is powered on and the noise signal is cancelled will not exceed 3 seconds. If the delay is too long, there will be an extended period of unpleasant ringing while the signals are not 180 degrees out of phase. If this period is excessively long, it could become unpleasant to the customer. 1,4 M. The volume of the counter signal will not exceed 85 dB. To produce a pleasant output sounds the counter signal must be relatively inaudible by humans. Also, the system should never produce a sound that could be painful or cause harm to the customers’ ears. 13 N. The system must be able to interact with two microphone inputs either through line inputs or GPIO pins. This is a fundamental part of the system’s operation. The system must be able to take in the noisy signal and have a feedback loop for the algorithm to work.

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12 MicrophoneI2S Connections

13 Pin 39: SCK Pin 40: SD Pin 61: WS Xilinx Virtex 5

14 Audio Codec

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16 Component DescriptionCostOur CostAvailability Omnidirectional Microphone $3.23$0.60 In stock from InvenSense. Inc/485883&pid=1135 Part Number: INMP441ACEZ Lead Time: 4-5 business days Surface-mount PCB Capacitors $0.43 In stock from DigiKey. Part Number: ND Lead Time: 3 business days Surface-mount PCB Resistors $1.15 In stock from DigiKey. Part Number: MCS K-CFCT-ND Lead Time: 3 business days

17 Component DescriptionCostOur CostAvailability Superlux HD668B Headphone $43.82$0.00 In stock from Amazon. Headphones/dp/B003JOETX8 Part Number: NA Lead Time: 3-5 business days Xilinx Virtex-5 XC5VLX110T $2, or $ (Academic) $0.00 In stock from Digilent. &Nav2=Programmable Part Number: P-KIT Lead Time: 2-3 business days Total Cost $2, or $847.63$2.18

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19 Engineering Requirement Test DescriptionExpected Result Pass/Fail Unit Testing C The purpose of this test is to test the Matlab version of the LMS algorithm. Since the Matlab software has already been verified, the algorithm will be verified by code inspection by a team member who did not write the Matlab code. The Matlab code should accurately model the operations required by the LMS algorithm. C The purpose of this test is to test the Matlab version of the FIR filter. Since the Matlab software has already been verified, the filter will be verified by code inspection by a team member who did not write the Matlab code. The Matlab code should accurately model the operations required by the FIR filter. C The purpose of this test is to test the HDL description of the FIR filter using a VHDL testbench. Stimulus and expected output data can be generated by the Matlab model. The output HDL description matches the expected output.

20 Engineering Requirement Test DescriptionExpected ResultPass/Fail Unit Testing C The purpose of this test is to test the HDL description of the LMS algorithm using a VHDL testbench. Stimulus and expected output data can be generated by the Matlab model. The output HDL description matches the expected output. C, D The purpose of this test is to test the Audio Codec on the board. A sinusoid will be generated and passed through the Audio Codec to verify that it is functioning as expected. The sinusoid will be heard through the plugged in headset. N The purpose of this test is to test the I2S protocol library using a VHDL testbench. The testbench will act as a SLAVE to ensure the communication protocol is functioning properly. The I2S protocol functions as expected.

21 Engineering Requirement Test DescriptionExpected ResultPass/Fail Unit Testing N The purpose of this test is to test the microphones use of the I2S protocol. This will be accomplished by applying a 2.82 MHz clock to SCK, applying a 44.1 KHz clock to WS, driving L/R high, and driving CHIPEN to high. The clocks will be generated by the FPGA. The output will be monitored on an oscilloscope. The microphone is using the I2S protocol as expected. Integration Testing C The purpose of this test is to test the hierarchical MATLAB model. This will be accomplished through testing all the modules of the system by driving the input signal. The system as a whole functions as expected. C The purpose of this test is to test the integrated HDL description of the noise cancellation module using a VHDL testbench. Stimulus and expected output can be generated by the Matlab model. The output HDL description matches the expected output.

22 Engineering Requirement Test DescriptionExpected ResultPass/Fail Integration Testing N The purpose of this test is to test the integration of the microphone and the Audio Codec. The FPGA will be configured to send the audio data from the microphone directly to the Audio Codec. Audio detected by the microphone is passed through the Audio Codec without distortion. C, K The purpose of this test is to ensure that the algorithm works on the FPGA. The adaptive noise system as a whole will be connected and tested for noisy input signals in the frequency range of 420 Hz to 460 Hz. At least 20 individuals will be polled to determine if there is a noticeable drop in volume. There has been a noticeable drop in volume.

23 Engineering Requirement Test DescriptionExpected ResultPass/Fail Acceptance Testing D The purpose of this test is to test the successful output of a signal to the headphones. The input signal will be sent through the Audio Codec, through the 3.5 mm jack, and to the headset. A clear audio signal is produced by the headset. A The purpose of this test is to test the accessibility of the on/off switch. The switch will be pressed to test it. The system powers on/off as expected. B The purpose of this test is to review the system documentation for completeness. This includes comments in the MATLAB code and the VHDL description. The document is thorough.

24 Engineering Requirement Test DescriptionExpected ResultPass/Fail Acceptance Testing D The purpose of this test is to ensure the 3.5 mm headphone jack is accessible to the user. Plug the headphones in to ensure the 3.5 mm jack is accessible to the user. The 3.5 mm jack is accessible to the user. E Review the necessary components and ensure the total cost of the system does not exceed $1000. The system cost does not exceed $1000. F This test verifies that the system dimensions are within the required dimensions. The dimensions of the case will be measured to ensure the system will fit in the enclosure. The enclosure is no more than two inches larger than the FPGA on any side. F This test verifies the safety of the system. The enclosure will be checked for sharp edges or exposed wires. The enclosed system has no sharp edges or exposed wires.

25 Engineering Requirement Test DescriptionExpected ResultPass/Fail Acceptance Testing F This test verifies that the system is aesthetically pleasing to a majority of potential users. At least 10 individuals will be polled to gather feedback on the aesthetics of the system. At least 80% of the individuals polled agree that the system is aesthetically pleasing compared to a board with no enclosure. H The purpose of this test is to test that the 60 Hz sine wave and a 15 kHz sine wave can be detected by the microphones and monitored on an oscilloscope. The sine waves are successfully viewed on the oscilloscope. I, J This test verifies that the system's total energy usage is within the required usage. A watt-meter will be used to monitor the instantaneous power and the total energy in kilowatt-hours over a 12 hour period. The instantaneous power is less than ten watts and the total energy in kilowatt- hours is less than 0.3 kilowatt- hours.

26 Engineering Requirement Test DescriptionExpected Result Pass/Fai l Acceptance Testing L This test verifies the noise range countered by the system. The system will be tested with frequencies in the band 420 Hz to 460 Hz, in increments of 10 Hz, to ensure cancellation of the signals within 3 seconds. This will be measured using a stopwatch. The system successfully counters all tones in the frequency band within the 3 second window. M This test verifies that the gain of the system output is below the required threshold. Sensors will be used to measure an ambient noise and the output signal for the frequency band of 60 Hz to 15 kHz. This will be used to calculate the output dB of the system. (The sensor type is still to be determined, but we could possibly use a standard computer microphone.) The system produces output signals that are below 85 dB. C This test verifies that the functional algorithm counter frequencies in the band 420 Hz to 460 Hz. This will be accomplished by sending these frequencies through our functional MATLAB simulation and listening to the output file. There has been a noticeable drop in volume.

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