ECE692 Course Project Proposal Cache-aware power management for multi-core real-time systems Xing Fu Khairul Kabir 16 September 2009

Background Thermal and power problems of single processor ▫ Multi-core architectures as a solution Most existing work on general-purpose computing system ▫ few work focus on multi-core real-time system. Shared L2 cache is a performance bottleneck. ▫ L2 cache thrashing can cause deadline miss. ▫ Multi-core real-time systems should be cache-aware. New architecture feature – cache resizing can be exploited. ▫ Example, the Intel ® Advanced Smart Cache Most existing work consider real-time guarantee and power management in separation.

Related Work Open-loop real-time scheduling schemes for multi-core system ▫ L2 cache trashing avoiding scheduling [Anderson 06] ▫ Encourage the co-scheduling of tasks [Calandrino 08]  ALL assume accurate knowledge of execution time Utilization Control ▫ Extensive works on utilization control ▫ Examples, [Fu 09][Wang 09][Wang 07][Lu 03][Stankovic 01]  Only for single-processor and multi-processor control  An assumption does not hold for cache-aware multi-core real- time. Few work considering both real-time guarantee and power/thermal management. ▫ Minimized peak temperature and guarantee real-time [Fisher 09]

Description of the Project Utilization control ▫ Extend system models used in existing work on utilization control.  The estimated one core CPU utilization is related to core frequency and the L2 cache size allocated to the core.  The control goal is to minimize the difference between core utilization set point and measured core utilization by manipulating core frequency and the L2 cache size.  The control problem can be formulated as a MIMO MPC problem because the core utilizations are not independent due to shared L2 cache. Power management ▫ Adapt core frequency to workload requirement. ▫ Turn off idling L2 caches to reduce power consumption.

Goals Formulate the problem as a MPC problem with constraints. Transform the MPC problem to standard format. Analyze control performances. Evaluate our solution by experiment or simulation. Compare our result with certain baselines.

Challenges How to derive system model? ▫ Specifically, the relationship between core utilizations and the L2 cache size allocated to the core. Possible approaches includes:  (1) Search general propose computing papers,  Multi-Optimization Power Management for Chip Multiprocessors [Meng 08],  Performance of Multithreaded Chip Multiprocessors And Implications [Fedorova 05]  (2) System identification How to evaluate our solution? ▫ Hardware, simulator and architecture-level simulator.  Issues with each methods. ▫ Hybrid simulation

Any comments and critiques are welcomed! Xing Fu Khairul Kabir