Optical Readout Interface (ORI)

Slides:



Advertisements
Similar presentations
1 IWORID 2002 David San Segundo Bello Design of an interface board for the control and data acquisition of the Medipix2 chip D. San Segundo Bello a,b,
Advertisements

LOGSYS Development Environment of Embedded Systems Tamás Raikovich Béla Fehér Péter Laczkó Budapest University of Technology and Economics Department of.
Token Bit Manager for the CMS Pixel Readout
E-link IP for FE ASICs VFAT3/GdSP ASIC design meeting 19/07/2011.
Richard Kass IEEE NSS 11/14/ Richard Kass Radiation-Hard ASICs for Optical Data Transmission in the ATLAS Pixel Detector K.E. Arms, K.K. Gan, M.
CHAPTER 1 Digital Concepts
Outer Tracker Electronics ASD TDC L0 Buffer L1 Buffer biasL0 BXL1 50 fC DAQ chambercounting room ~100m Ulrich Uwer University of Heidelberg LHCC Review.
SVT TDR meeting – March 30, 2012 List of peripheral blocks for SVT strip readout chips.
David Nelson STAVE Test Electronics July 1, ATLAS STAVE Test Electronics Preliminary V3 Presented by David Nelson.
Development of an ATCA IPMI Controller Mezzanine Board to be used in the ATCA developments for the ATLAS Liquid Argon upgrade Nicolas Dumont Dayot, LAPP.
Beam Position Monitors: Front-End Components - BPM Acquisition Architecture - Components Selection - Irradiation Tests MOPOS Radiation Tests - JL Gonzalez.
Time Division Multiplexing School of Physics and Astronomy Department of Particle Physics Elissavet Papadima 29/5/2014.
LECC03, 9/30/2003 Richard Kass/OSU 1 Richard Kass Radiation-Hard ASICs for Optical Data Transmission in the ATLAS Pixel Detector K.E. Arms, K.K. Gan, M.
Semiconductors and Diodes
Mathieu Goffe EUDET JRA1 meeting, DESY Wednesday 30 January 2008 IPHC, 23 rue du Loess BP 28, 67037, Strasbourg Cedex 02, France.
Total Power Consumed by an Entire Opto-electronic Link.
SPS Beam Position Monitors: MOPOS Front-End Electronics Jose Luis Gonzalez BE/BI 22/11/2013.
US CMS Collaboration Meeting, May 19, PWO Crystal ECAL Ren-yuan Zhu California Institute of Technology May 19 th 2001.
ISUAL Sprite Imager Electronic Design Stewart Harris.
MPPC R&D status Kobe Univ. CALICE collaboration meeting Yuji SUDO Univ. of Tsukuba ~ contents ~ Introduction Linearity curve Recovery time.
Electronics for PS and LHC transformers Grzegorz Kasprowicz Supervisor: David Belohrad AB-BDI-PI Technical student report.
DCS Detector Control System Hardware Dirk Gottschalk Volker Kiworra Volker Lindenstruth Vojtech Petracek Marc Stockmeier Heinz Tilsner Chair of Computer.
Uni-Heidelberg, KIP, V.Angelov 1 International Workshop TRDs – Present & Future September, Romania Wafer Tester, Optical Link, GTU V. Angelov Kirchhoff.
SODA: Synchronization Of Data Acquisition I.Konorov  Requirements  Architecture  System components  Performance  Conclusions and outlook PANDA FE-DAQ.
LNL 1 SLOW CONTROLS FOR CMS DRIFT TUBE CHAMBERS M. Bellato, L. Castellani INFN Sezione di Padova.
Irradiation Test of the Omegapix2 Digital Tier May 18-22, 2015, CERN Olivier Le Dortz, LPNHE Paris Juin 2015.
Phase-1 Design. i PHC Phase /04/2008 System Overview Clock, JTAG, sync marker and power supply connections Digital output.
Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use ECE/CS 352: Digital Systems.
FE Electronics - Overview ASD TDC L0 Buffer L1 Buffer biasL0 BXL1 50 fC DAQ counting room ~100m FE Electronics on the detector GOL Electronics Service.
Optical Links CERN Versatile Link Project VL – Oxford involvement CERN VL+ for ATLAS/CMS phase II upgrade – Introduction and aims – Oxford workpackage:
ELE2MIC Lecture 19 MULTIPLEXOR - DATA SELECTOR
FED RAL: Greg Iles5 March The 96 Channel FED Tester What needs to be tested ? Requirements for 96 channel tester ? Baseline design Functionality.
Characterization of Semiconductor Lasers for Radiation Hard High Speed Transceivers Sérgio Silva, Luís Amaral, Stephane Detraz, Paulo Moreira, Spyridon.
Optical Readout and Control Interface for the BTeV Pixel Vertex Detector Optical interface for the PCI board –1.06 Gbps optical link receiver –Protocol.
NUMI Off Axis NUMI Off Axis Workshop Workshop Argonne Meeting Electronics for RPCs Gary Drake, Charlie Nelson Apr. 25, 2003 p. 1.
Michał Dwużnik, for the SCT collaboration
December 14, 2006Anuj K. Purwar1 Design proposal for Read Out Card (ROC) Anuj K. Purwar December 14, 2006 Nevis Meeting.
WP5 – Wirespeed Photonic Firewall Validation Start M27, finish M35 Avanex lead Description of Work –Establish test bed suitable to validated the optical.
ERC - Elementary Readout Cell Miguel Ferreira 18 th April 2012
Implementing a 10 Gb/s VCSEL Driven Transmitter for Short Range Applications Irfan N. Ali Michael C. Clowers David S. Fink Sean K. Garrison Jeff A. Magee.
FEC electronicsRD-51 mini week, CERN, Sept Towards the scalable readout system: FEC electronics for APV25, AFTER and Timepix J.
December Status of MRS photodiodes ND280 Convener’s Meeting, 9 June 2006 Yury Kudenko INR, Moscow.
.1PXL READOUT STAR PXL READOUT requirement and one solution Xiangming Sun.
Dirk Wiedner 16 th February OT/ITCALO MUON RICH1/TT RICH2 +TFC system.
Opto Working Group Meeting Summary Tuesday 8 March 2011 Tobias Flick and Francois Vasey.
J. Ye SMU Joint ATLAS-CMS Opto-electronics working group, April 10-11, 2008 CERN 1 Test Results on LOC1 and Design considerations for LOC2 LOC1 test results:
Marc R. StockmeierDCS-meeting, CERN DCS status ● DCS overview ● Implementation ● Examples – DCS board.
Readout controller Block Diagram S. Hansen - CD-1 Lehman Review1 VXO Ø Det Links to 24 SiPM Front End Boards Clock Event Data USB ARM uC A D Rd Wrt 100Mbit.
June 2004 Craig Ogilvie 1 Strip Pilot  Communication link between ladder and counting house  Three optical fibers –Send serialized data –Receive control.
A versatile FPGA based photon counter and correlator sudersan dhep meet’16.
PicoTDC architecture & Readout Jorgen Christiansen, PH-ESE 1.
Electronics Department Amsterdam 5-July-2010 Sander Mos 1 Status and progress of NIK* Logic WPFL - 5 July 2010 Amsterdam * Network Interface Kit.
DOM Electronics (Digital Optical Module) 1 WPFLElectronics PPMDOM ElectronicsF. Louis.
Gigabit Ethernet – IEEE 802.3z The Choice of a New Generation Design Presentation ECE 4006c G2- Gigabit Ethernet Intel/Agilent TX Javier Alvarez, gte006r.
MICROCONTROLLER AND INTERFACING Presented by: Shefali Jethva ( ) Shivali Panchal ( ) Komal Soni ( ) Roll no. :- 14EC308.
THE MOST SUCCESSFUL C2000 MCU
Configuration and local monitoring
DAQ read out system Status Report
The Data Handling Hybrid
Test Boards Design for LTDB
ISUAL Imager Stewart Harris.
Next generation rad-hard links
CPU1 Block Specifications
The Data Handling Hybrid
96-channel, 10-bit, 20 MSPS ADC board with Gb Ethernet optical output
TTC system for FP420 reference timing?
ECE 4006 CAPSTONE DESIGN R.Y.M.M.Y Georgia Institute of Technology
Surface emitting diode laser
New DCM, FEMDCM DCM jobs DCM upgrade path
TPC Electronics Meeting, 13/01/05 Carmen González Gutiérrez
Presentation transcript:

Optical Readout Interface (ORI) latency +24 ns +24 ns +300 ns Conf. Mem. 125MHz 120MHz 8 bit DDR I2C SERDES 2.5GBits/s Laser Driver CPLD HCM (TRAP) LVDS-TTL 16 DDR SDR Resynchronization, status, counters VCSEL Laser Diode 850 nm

ORI – production test (laser diode) Several parameters controlled: Supply currents at various operation mode conditions Voltages on the board in enabled/disabled state Source, bias and modulation currents through the laser diode Temperature of the laser driver chip optical output power photodiode current measured by the laser driver chip

No permanently damaged components. Equivalent time in years in blue, No permanently damaged components. Equivalent time in years in blue, * - the device fails. Recovery after power cycle or switching off for up to 12 hours (VR and Laser Driver). The configuration of the CPLD and EEPROM was not damaged. Laser Driver Linear Technology LTC5100 100* VCSEL Diode ULM Photonics ULM850-02-LC-TOSA 20 EEPROM 24LC01 30* LVDS Transceiver National Semiconductor DS90LV048A 30 CPLD Lattice LC4256V 15-50* Serializer Texas Instruments TLK2501 250* Voltage Regulators National Semicondutor LP3962-3.3 and -2.5 60-110* F.Rettig

CLK C D Q Q A Y0 Y1 Y2 Y3 E D Q GCNTp decoder 4:1 mux with gray encoding GCNTc STROBE IN DATA GREG B A=B comp Falling edge data OUT DATA VALID