CEC 220 Digital Circuit Design Implicants Wed, Sept. 23 CEC 220 Digital Circuit Design Slide 1 of 10.

Slides:



Advertisements
Similar presentations
Techniques for Combinational Logic Optimization
Advertisements

Chapter 3 Gate-Level Minimization
Gate-Level Minimization
Chapter 3 Simplification of Switching Functions. Karnaugh Maps (K-Map) A K-Map is a graphical representation of a logic function’s truth table.
Gate-level Minimization
©2004 Brooks/Cole FIGURES FOR CHAPTER 5 KARNAUGH MAPS Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter in the.
CSCE 211: Digital Logic Design Chin-Tser Huang University of South Carolina.
Give qualifications of instructors: DAP

Computer Engineering (Logic Circuits) (Karnaugh Map)
ECE 331 – Digital System Design Karnaugh Maps and Determining a Minimal Cover (Lecture #7) The slides included herein were taken from the materials accompanying.
ECE 301 – Digital Electronics Karnaugh Maps and Determining a Minimal Cover (Lecture #8) The slides included herein were taken from the materials accompanying.
CS 140 Lecture 5 Professor CK Cheng CSE Dept. UC San Diego 1.
Simplifying Boolean Expressions Using K-Map Method
1 Simplification of Boolean Functions:  An implementation of a Boolean Function requires the use of logic gates.  A smaller number of gates, with each.
1 Chapter 5 Karnaugh Maps Mei Yang ECG Logic Design 1.
Chapter 3 Simplification of Switching Functions. Simplification Goals Goal -- minimize the cost of realizing a switching function Cost measures and other.
The covering procedure. Remove rows with essential PI’s and any columns with x’s in those rows.
ES 244: Digital Logic Design Chapter 3 Chapter 3: Karnaugh Maps Uchechukwu Ofoegbu Temple University.
Examples. Examples (1/11)  Example #1: f(A,B,C,D) =  m(2,3,4,5,7,8,10,13,15) Fill in the 1’s. 1 1 C A B CD AB D 1 1.
Karnaugh map minimization Basic Terms (1) minterm maxterm - a single 1 - a single 0 1. implicant
Unit 5 Karnaugh Maps Fundamentals of Logic Design by Roth and Kinney.
PRASAD A. PAWASKAR SPN. NO DETE 2 SEMESTER lec1-11.
Converting to Minterms Form
Computer Engineering (Logic Circuits) (Karnaugh Map)
Karnaugh Maps ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.
Chapter3: Gate-Level Minimization Part 1 Origionally By Reham S. Al-Majed Imam Muhammad Bin Saud University.
CS2100 Computer Organisation
THE K-MAP.
Karnaugh Maps (K-Map) A K-Map is a graphical representation of a logic function’s truth table.
1 Example: Groupings on 3-Variable K-Maps BC F(A,B,C) = A ’ B ’ A BC F(A,B,C) = B ’ A
CEC 220 Digital Circuit Design NAND/NOR Multi-Level Circuits
Digital Logic (Karnaugh Map). Karnaugh Maps Karnaugh maps (K-maps) are graphical representations of boolean functions. One map cell corresponds to a row.
Lecture # 5 University of Tehran
Karnaugh Maps (K maps).
CEC 220 Digital Circuit Design More Karnaugh Maps Monday, February 02 CEC 220 Digital Circuit Design Slide 1 of 11.
EECS 270 Lecture 10. K-map “rules” – Only circle adjacent cells (remember edges are adjacent!) – Only circle groups that are powers of 2 (1, 2,
School of Computer and Communication Engineering, UniMAP DKT 122/3 - DIGITAL SYSTEM I Chapter 4A:Boolean Algebra and Logic Simplification) Mohd ridzuan.
CEC 220 Digital Circuit Design Minterms and Maxterms Monday, January 26 CEC 220 Digital Circuit Design Slide 1 of 11.
Chapter 3 Simplification of Switching Functions. Simplification Goals Goal -- minimize the cost of realizing a switching function Cost measures and other.
©2010 Cengage Learning SLIDES FOR CHAPTER 5 KARNAUGH MAPS Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter.
ECE 2110: Introduction to Digital Systems
Lecture #6 EGR 277 – Digital Logic
ECE 3110: Introduction to Digital Systems
CSE 140: Components and Design Techniques for Digital Systems
CS 352 Introduction to Logic Design
CSCE 211: Digital Logic Design
ECE 2110: Introduction to Digital Systems
CPE/EE 422/522 Advanced Logic Design
ECE 331 – Digital System Design
Digital Logic and Design
CSCE 211: Digital Logic Design
CSCE 211: Digital Logic Design
ECE 616 Advanced FPGA Designs
ECE 434 Advanced Digital Systems
CSCE 211: Digital Logic Design
CSCE 211: Digital Logic Design
Digital Logic & Design Dr. Waseem Ikram Lecture 12.
EECS 465: Digital Systems Lecture Notes # 2
Digital Logic & Design Dr. Waseem Ikram Lecture 13.
CHAPTER 5 KARNAUGH MAPS 5.1 Minimum Forms of Switching Functions
CSE 140: Components and Design Techniques for Digital Systems
CH7 Multilevel Gate Network
Chapter 3 Gate-level Minimization.
CSCE 211: Digital Logic Design
Overview Part 2 – Circuit Optimization
3-Variable K-map AB/C AB/C A’B’ A’B AB AB’
Professor CK Cheng CSE Dept. UC San Diego
CSCE 211: Digital Logic Design
Simplification of Boolean Functions using K-Maps
Presentation transcript:

CEC 220 Digital Circuit Design Implicants Wed, Sept. 23 CEC 220 Digital Circuit Design Slide 1 of 10

Lecture Outline Wed, Sept. 23 CEC 220 Digital Circuit Design Implicants Prime Implicants Essential Prime Implicants Slide 2 of 10

Four Variable Karnaugh Maps Implicants and Prime Implicants Wed, Sept. 23 CEC 220 Digital Circuit Design Implicants  A single 1 or group of 1’s which can be combined to form a simpler term is called an implicant AB CD Slide 3 of 10

Four Variable Karnaugh Maps Implicants and Prime Implicants Wed, Sept. 23 CEC 220 Digital Circuit Design Prime Implicants  An Implicant which can NOT be combined into another block is called a prime implicant AB CD Slide 4 of 10

Four Variable Karnaugh Maps Implicants and Prime Implicants Wed, Sept. 23 CEC 220 Digital Circuit Design Prime Implicants  An Example AB CD All Prime Implicants: Min SOP Expression: Not all Prime Implicants are essential!! Slide 5 of 10

Four Variable Karnaugh Maps Implicants and Prime Implicants Wed, Sept. 23 CEC 220 Digital Circuit Design Essential Prime Implicants  If a minterm is covered by only one prime implicant then that prime implicant is an essential prime implicant. AB CD Essential Prime Implicants? Min SOP Expression: Essential Prime Implicants MUST be included in the min SOP expression Slide 6 of 10

Karnaugh Maps Flowchart for Determining the min SOP Expression Wed, Sept. 23 CEC 220 Digital Circuit Design All uncovered 1’s checked? Are the chosen 1 and its adjacent 1’s and X’s covered by a single term? Are the chosen 1 and its adjacent 1’s and X’s covered by a single term? Find a minimum set of prime implicants which cover the remaining 1’s on the map. Find a minimum set of prime implicants which cover the remaining 1’s on the map. That term is an essential prime implicant. Circle it. Find all adjacent 1’s and X’s. Choose a 1 which has not been covered. yes no Start Slide 7 of 10

Karnaugh Maps Flowchart for determining the minimum SOP Wed, Sept. 23 CEC 220 Digital Circuit Design An Example Essential Prime Implicants: Slide 8 of 10

Karnaugh Maps Flowchart for determining the minimum SOP Wed, Sept. 23 CEC 220 Digital Circuit Design An Example Essential Prime Implicants: Slide 9 of 10

Next Lecture Wed, Sept. 23 CEC 220 Digital Circuit Design Multi-Level Gate Circuits Slide 10 of 10

Feedback: Privacy Policy Feedback
Do Not Sell My Personal Information
About project: SlidePlayer Terms of Service

© 2024 SlidePlayer.com Inc. All rights reserved.