1 ECE 545 – Introduction to VHDL Algorithmic State Machines Sorting Example ECE 656 Lecture 8

2 ECE 545 – Introduction to VHDL Sources & Required Reading Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 8.10 Algorithmic State Machine (ASM) Charts Chapter Sort Operation

3 ECE 545 – Introduction to VHDL Algorithmic State Machine (ASM) Charts

4 ECE 545 – Introduction to VHDL Algorithmic State Machine Algorithmic State Machine – representation of a Finite State Machine suitable for FSMs with a larger number of inputs and outputs compared to FSMs expressed using state diagrams and state tables.

5 ECE 545 – Introduction to VHDL Elements used in ASM charts (1) Output signals or actions (Moore type) State name Condition expression 0 (False) 1 (True) Conditional outputs or actions (Mealy type) (a) State box(b) Decision box (c) Conditional output box

6 ECE 545 – Introduction to VHDL Elements used in ASM charts (2) State box – represents a state. Equivalent to a node in a state diagram or a row in a state table. Moore type outputs are listed inside of the box. It is customary to write only the name of the signal that has to be asserted in the given state, e.g., z instead of z=1. Also, it might be useful to write an action to be taken, e.g., Count = Count + 1, and only later translate it to asserting a control signal that causes a given action to take place.

7 ECE 545 – Introduction to VHDL Elements used in ASM charts (3) Decision box – indicates that a given condition is to be tested and the exit path is to be chosen accordingly The condition expression consists of one or more inputs to the FSM. Conditional output box – denotes output signals that are of the Mealy type. The condition that determines whether such outputs are generated is specified in the decision box.

8 ECE 545 – Introduction to VHDL Moore FSM – Example 1: State diagram Cz1=  Reset Bz0=  Az0= w0= w1= w1= w0= w0= w1=

9 ECE 545 – Introduction to VHDL ASM Chart for Moore FSM – Example 1

10 ECE 545 – Introduction to VHDL A w0=z0=  w1=z1= B w0=z0= Reset w1=z0=  Mealy FSM – Example 2: State diagram

11 ECE 545 – Introduction to VHDL ASM Chart for Mealy FSM – Example 2

12 ECE 545 – Introduction to VHDL Control Unit Example: Arbiter (1) Arbiter reset r1 r2 r3 g1 g2 g3 clock

13 ECE 545 – Introduction to VHDL Idle 000 1xx Reset gnt1g 1  1= x1x gnt2g 2  1= xx1 gnt3g 3  1= 0xx1xx 01xx0x 001xx0 Control Unit Example: Arbiter (2)

14 ECE 545 – Introduction to VHDL Control Unit Example: Arbiter (3)

15 ECE 545 – Introduction to VHDL ASM Chart for Control Unit - Example 3

16 ECE 545 – Introduction to VHDL Digital System Design with VHDL

17 ECE 545 – Introduction to VHDL Structure of a Typical Digital System Execution Unit (Datapath) Control Unit (Control) Data Inputs Data Outputs Control Inputs Control Outputs Control Signals

18 ECE 545 – Introduction to VHDL Hardware Design with RTL VHDL Pseudocode Execution Unit Control Unit Block diagram Block diagram ASM VHDL code Interface

19 ECE 545 – Introduction to VHDL Sorting

20 ECE 545 – Introduction to VHDL Sort Clock Resetn DataIn N DataOut N Sorting - Required Interface Done RAdd L WrInit S (0=initialization 1=computations) Rd

21 ECE 545 – Introduction to VHDL Simulation results for the sort operation (1) Loading the registers and starting sorting

22 ECE 545 – Introduction to VHDL Simulation results for the sort operation (2) Completing sorting and reading out registers

23 ECE 545 – Introduction to VHDL Sorting - Example Before sorting During Sorting After sorting address i=0i=0i=0i=1i=1i=2 j=1j=2j=3j=2j=3j=3 RiRi RjRj Legend: position of memory indexed by i position of memory indexed by j

24 ECE 545 – Introduction to VHDL Pseudocode for the sort operation for i=0 to k2 do A=R i ; for j=i+1 to k1 do B=R j ; if B<A then R i =B ; R j =A ; A=R i ; end if; end for; – –