PC Based Spectrum Analyzer April 29, 2003 May03-10 Faculty Advisor: Dr. DJ Chen Michael Cain Paul Heil Eric Rasmussen Aung Thuya Client: Teradyne Inc. Phase III
The team would like to thank: Teradyne Steve Miller Dr. Degang Chen Acknowledgements
Problem Statement Operating Environment Intended Use and Users Assumptions and Limitations End Product Accomplishments Approaches Research Design Implementation Testing Resources and Schedules Closing Materials Presentation Outline
List of Definitions DAC – digital to analog converter DC offset – DC voltage in an AC signal FPGA – field programmable gate array Spectrum analyzer – measures magnitude of signal harmonics THD – total harmonic distortion
100MHz high gain, low noise, low distortion Programmable DC offset and frequency response calibration Amplifier for PC Based Spectrum Analyzer Problem Statement
DC — 1kHz+/- 5 volts6, 20, 40, 60+/- 10 volts0.05 dB< dB1.5 nV/rtHz > 1kHz - 20 kHz+/- 5 volts6, 20, 40, 60+/- 10 volts0.05 dB< - 95 dB1.5 nV/rtHz > 20kHz - 100kHz+/- 2.5 volts6, 20, 40+/- 5 volts0.10 dB< -85 dB2.5 nV/rtHz > 100kHz - 1MHz+/- 2.5 volts6, 20, 40+/- 5 volts0.10 dB< - 80 dB3.5 nV/rtHz > 1MHz - 10MHz+/- 2.5 volts6, 20, 40+/- 5 volts0.10 dB< - 70 dB3.5 nV/rtHz > 10MHz - 20MHz+/- 2.5 volts6, 20+/- 5 volts0.10 dB< -65 dB3.5 nV/rtHz > 20MHz - 50MHz+/- 1.0 volts6, 20+/- 2.0 volts0.10 dB< -50 dB5.0 nV/rtHz > 50MHz - 100MHz+/- 1.0 volts6, 20+/- 2.0 volts0.10 dB< -40 dB5.0 nV/rtHz Input Total InputVoltageAvailableMax Output Freq ResponseHarmonic FrequencyRange Gain SettingsVoltageFlatnessDistortionNoise Range(Volts)(dB)(Volts)(dB) (nV/rtHz) Problem Statement (cont’d.)
Normal lab conditions Low humidity, room temperature Operating Environment
Intended Users and Uses Users will be Teradyne test engineers Use will be preamplifier for PC Based spectrum analyzer
Users Teradyne test engineers are familiar with the operation of a spectrum analyzer Requirements Specifications are attainable Financial Budget Teradyne will cover project costs Assumptions
Hardware Noise and distortion trade-off Must have a stable configuration Software Simulation software limitations Technical Knowledge No experience with PC board fabrication Limitations
The end product will consist of the following deliverables: Analog amplifier design with embedded digital controls Software for the embedded digital controls Design and user documentation End Product
Research – 100% completed Analog amplifier design – 100% completed Digital controls – 100% completed Software controls – 100% completed Simulations – 100% completed Fabrication – 0% completed Testing – 0% completed Present Accomplishments
Amplifier Topology Low noise amplifier (LNA) Operational amplifier in resistive feedback Approaches Considered and Used
DC Offset Correction Clocked ping-pong structure Offset voltage referral Successive approximation scheme Approaches Considered and Used (cont’d.)
Frequency Response Calibration Automatic Manual Approaches Considered and Used (cont’d.)
Project Definition Activities Project scope was changed to a paper design Occurred after design was submitted for fabrication Will be completed by future team
Amplifier Topologies Operational Amplifiers DACs FPGAs Digital Potentiometers Comparators Research Activities
Amplifier Design Design Activities
Design Activities (cont’d.)
DC offset correction Design Activities (cont’d.)
Frequency response calibration
Design Activities (cont’d.)
Implementation Activities Implementation was not necessary
PSpice simulations for analog design Verilog simulations for digital state machine Testing Activities
Other Significant Activities User manual Estimated performance analysis Design vault on CD
Resource Requirements Personal Effort
Resource Requirements (cont’d.) ItemTeam HoursOther HoursCost Board Fabrication00$0 Components00$0 Project Poster100$48 Total100$48 Total Cost
Project Schedule Schedule
Schematic level implementation – fully met Simulations – fully met Fabrication – not attempted Testing – not attempted Project Evaluation
Only one will be fabricated for testing purposes Will be a part of Teradyne’s Integra J750 Cost of J750 starts at $99,000 Commercialization
Meet low noise requirement Make frequency response calibration automatic Fabricate board Complete testing Recommendations for Future Work
Set up weekly meetings with client and team Do not procrastinate Make sure design tools are adequate Do not be too optimistic with scheduling Do not be too elaborate with complicated designs Lessons Learned
Losing a team member No available times for meetings Parts ordered on time Sending design to fabrication on time Risk and Risk Management
Closing Summary Learned a lot about amplifier topologies Team skills improved Useful information passed to next group
Questions?