Final Review Prof. Mike Schulte Advanced Computer Architecture ECE 401

Final Review Material Covered –Chapters 1-3 of textbook (about 30%) –Chapters 4 and 5 - of textbook (about 70%) –Associated homework problems –3 research articles »Instruction Issue Logic for High-Performance Interruptable Pipelined Processors (CH3) »Complexity-effective Superscalar Processors (CH4) »Virtual Memory in Contemporary Microprocessors (CH5) Format –Open everything (notes, books, papers, calculator) –3 hours to complete - Dec 18, 8:00 to 11:00 AM, PL 466 –5 to 10 questions (multiple parts) –Similar to ECE401 midterm

Advanced Pipelining and ILP Important material from Chapter 4 includes –Pipeline scheduling and loop unrolling –Dependencies (data, name, control) –Dynamic scheduling (scoreboarding and Tomasulo) –Dynamic branch prediction (BHT, correlating predictors, branch target buffers) –Multiple instruction issue (Superscalar and VLIW) –Compiler support for ILP (software pipelining, eliminating dependencies) –Hardware support for ILP (poison bits, conditional instructions, hardware speculation) –Limits to ILP –The PowerPC 620

Memory Hierarchy Design Cache Design - block size, associativity, replacement policy, write policy. Cache Performance - AMAT Techniques for reducing –cache misses –miss penalty –hit time Main memory design Virtual memory - paging and segmentation Alpha APX memory hierarchy