1. Overview Prof. Eric Rotenberg
ECE 463/563 Fall `18
Overview
Prof. Eric Rotenberg
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

2. ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Computer Architecture & Systems
Computer Architecture
Processor Architecture (CPU, microprocessor)
Hard:
Correct & Fast CPU
Easy:
Correct CPU
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

3. Simple Processor Datapath
Register File 1 IF ID EX
MEM WB
(instr. fetch)
(instr. decode)
(execute)
(memory)
(writeback)
Memory (DRAM & Disk)
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

4. ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Pipelining
Invention #1
Register File IF
(instr. fetch) ID
(instr. decode) EX
(execute)
MEM
(memory) WB
(writeback) 4 5 6 3 1 2
Memory (DRAM & Disk)
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

5. Problem: Data-Dependent Instructions
Register File IF
(instr. fetch) ID
(instr. decode) EX
(execute)
MEM
(memory) WB
(writeback) 5 6 4 2 1 3
Memory (DRAM & Disk)
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

6. Register File Bypasses
Invention #2
Register File IF
(instr. fetch) ID
(instr. decode) EX
(execute)
MEM
(memory) WB
(writeback) 6 5 4 2 3 1
Flea-Flicker!
Memory (DRAM & Disk)
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

7. Problem: Branch Instructions
Register File 2 IF
(instr. fetch) ID
(instr. decode) EX
(execute)
MEM
(memory) WB
(writeback) 1 ? 2
Memory (DRAM & Disk)
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

8. ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Branch Prediction
Invention #3
Register File 2 3 4
Branch Predictor IF
(instr. fetch) ID
(instr. decode) EX
(execute)
MEM
(memory) WB
(writeback) 1 ? 2
Memory (DRAM & Disk)
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

9. Problem: “Memory Wall”
Register File
Branch Predictor IF
(instr. fetch) ID
(instr. decode) EX
(execute)
MEM
(memory) WB
(writeback)
Memory (DRAM & Disk)
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

10. ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Caches
Invention #4
Register File
Branch Predictor IF
(instr. fetch) ID
(instr. decode) EX
(execute)
MEM
(memory) WB
(writeback)
Instr. Cache
Data Cache
Memory (DRAM & Disk)
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

11. ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Caches (cont.)
Locality of reference
Temporal locality: If you access an item, likely to access it again in near future
Spatial locality: If you access an item, likely to access a nearby item in the near future
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

12. Problem: Stalled Instructions
Register File
Branch Predictor IF
(instr. fetch) ID
(instr. decode) EX
(execute)
MEM
(memory) WB
(writeback) 4 3 2 1
Instr. Cache
Data Cache
cache miss
Memory (DRAM & Disk)
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

13. Out-of-Order Execution
Invention #5
Register File
Branch Predictor IF
(instr. fetch) ID
(instr. decode) EX
(execute)
MEM
(memory) WB
(writeback) 4 6 5 7 3 2 1
Instr. Cache
Data Cache
Dynamic Scheduler
cache miss
Memory (DRAM & Disk)
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

14. Superscalar Execution
Register File
Branch Predictor 1 7 4 IF 5 2 8 ID EX
MEM WB
(instr. fetch) 9 6 3
(instr. decode)
(execute)
(memory)
(writeback)
Instr. Cache
Data Cache
Dynamic Scheduler
Memory (DRAM & Disk)
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

15. ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Deep Pipelining
Register File
Branch Predictor
IF1
IF2
ID1
ID2
EX1
EX2 M1 M2 W1 W2
Instr. Cache
Data Cache
Dynamic Scheduler
Memory (DRAM & Disk)
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

16. ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
OOO EXECUTION
SUPPORT
BRANCH PREDICTION
L1 Instr. Cache
L1 Data Cache
R.F. BYPASSES
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

17. ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Computer System
Application
ECE 209, 309
Operating
ECE 306, CSC 501
System
ECE 466/566
Compiler
Firmware
Computer Architecture = Instruction Set Architecture + Machine Organization
Instruction Set
Architecture
Machine Organization
ECE 109, 463/563
(ECE 506)
Processor
Mem.
I/O system
Datapath & Control
ECE 310, 464/564
ECE 212
Digital Design
ECE 211, 403
Circuit Design
ECE 546
Layout
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

18. ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Microarchitecture is often used to describe the “Processor” part of “Machine Organization”
Computer Architecture = Instruction Set Architecture + Machine Organization
Instruction Set
Architecture
Machine Organization
Processor
Mem.
I/O system
Microarchitecture
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

19. What is Computer Architecture?
Instruction Set Architecture +
Machine Organization
-- Capabilities & performance characteristics of principal Functional Units (FUs)
-- e.g., registers, ALUs, memory system, ...
-- Ways in which these components are interconnected
-- Choreography of components to realize the ISA
-- Performance-enhancing techniques and components
-- e.g., pipelining, caches, predictors, dynamic scheduling, superscalar execution, etc.
-- Programmable storage (registers, memory)
-- Data types and their encodings (integer, floating-point, SIMD, etc.)
-- Instruction Set
-- Instruction formats and encodings
-- Modes of addressing and accessing data and instructions
-- Exceptional conditions
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

20. ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Overview of Topics in 463/563
Measuring Performance and Cost
Caches and Memory Hierarchies
Instruction-Set Architecture (ISA)
Defines software/hardware interface
Simple Pipelining
Data and control (branch) dependencies
Register file bypasses
Branch prediction
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

21. ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Overview of Topics in 463/563
Complex Pipelining and Instruction-Level Parallelism (ILP)
Data hazards
Issue Queue (IQ): from in-order to out-of-order scheduling
Reorder Buffer (ROB): speculation and register renaming
Precise interrupts
Superscalar, VLIW, and vector processors
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

22. ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Projects
Three projects
Cache simulator
Branch predictor simulator
Superscalar pipeline simulator
Programming for projects is harder than anything many of you have encountered before
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

23. ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Course Grading
Breakdown
40% projects
10% homeworks (approx. 4 to 6 homeworks)
25% Midterm
Covers Performance/Cost, Caches
25% Final
Covers ISA, Simple & Complex Pipelining, ILP
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg

24. ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Course Web Page
wolfware.ncsu.edu
Login
Select ECE 463/563
Content
Syllabus (including my contact information and office hours)
Schedule
Homework and project handouts
etc.
Check frequently
Fall 2018
ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg