UK Bump Bonding (Flip-chip) Meeting at Daresbury (15th May): Tentative Agenda 10:00 Coffee Introduction and Welcome: Phil Allport (Liverpool) 10:40 Discussion of Requirements in Particle Physics 10:40 CMS: Mark Raymond (Imperial College) 10:50 ATLAS b-layer/3D: Cinzia da Via (Manchester) 11:00 ATLAS outer pixel: Craig Buttar (Glasgow) 11:10 LHCb: Themis Bowcock (Liverpool) 11:20 RD42 (Diamond Detectors): Joel Goldstein (Bristol) 11:30 RD50 (Rad-hard silicon): Gianluigi Casse (Liverpool) 11:40 Discussion of Requirements for Astrophysics and Space Science: Jon Lapington (Leicester) 12:00 Discussion of Requirements for Nuclear Physics: Ian Lazarus (DL, STFC) 12:20 Discussion of Synchrotron Applications: Nicola Tartoni (Diamond) 12:40 Discussion of Medical Physics Applications: Val O’Shea (Glasgow) 13:00 lunch 14:00 STFC Existing Bump-bonding Programme: John Lipp (RAL, STFC) 14:30 Discussion of Experience with Bump-bonding 14:30 Particle Physics: Richard Bates (Glasgow) 14:45 Astronomy and Astrophysics: Mike MacIntosh (UKATC, STFC) 15:00 Other Areas: John Lipp (RAL, STFC) 15:15 Tea 15:35 UK Requirements Discussion: Rich Farrow (DL, STFC) 16:00 Next Steps and Agreed Actions: Phil Allport (Liverpool) 16:30 Close

High density interconnect technologies are required in many scientific and engineering applications Many application areas require mega-pixel to giga-pixel scale imaging capability where a wire bond to every sense element is completely unfeasible (and geometrically excluded) Common solutions can be either to: a) Build a monolithic sensor with fully integrated read-out and sensing elements eg: i.CCDs ii.Active Pixel (CMOS) Sensors iii.SoI/3D interconnect/ (usually full wafer scale integration) b)Investigate flip-chip interconnect technologies i.Wafer-wafer, wafer-chip, chip-chip, prototyping ii.Naturally optimise sensor substrate separately from electronics iii.Use of non-silicon substrates Bump Bonding Requirements

The principle application has been to detect the passage of ionising radiation with high spatial resolution and good efficiency. Segmentation → position Depletion depth → efficiency ( W Depletion = {2ρμε(V ext + V bi )} ½ ) ~80e/h pairs/μm produced by passage of minimum ionising particle, ‘mip’ Resistivity Mobility Applied Voltage Pitch ~ 50  m Resolution: 5–10  m Highly segmented silicon detectors have been used in Particle Physics experiments for roughly 40 years Introduction to Silicon Detectors for HEP p + in n -

Nearly all early particle physics applications of silicon detectors were to detect and measure particles with pico-second ( ) lifetimes This meant the primary goal was to locate primary (collision) and secondary vertices (as is the case in LHCb) Material thickness (sensor +ASIC) must be minimised to reduce scattering Side on view of 7 TeV on 7 TeV proton collision Zoom in showing just particles from B S -meson decay Now also used as the primary charged particle tracking detectors for high radiation environments (eg CMS, ATLAS inner trackers, ALICE,...) p→ ←p γβcτ Highly Segmented Silicon Detectors

LHC vertex detectors closest to the interaction point: Technology in Current Highest Dose Regions ATLAS 100 million Pixels LHCb Vertex Locator Z(mm)=0-990 Required to be very radiation hard, thin as possible and have segmentation dictated by the very high density of tracks close to primary collisions Doses 5 – 10 × n eq cm -2 ≈ 100 Mrad (Future: n eq cm -2 ~Grad) 0.05mm ×0.4mm pixels (40 million images per second)

Current ATLAS Pixel Module → IBL: Single chip pixel modules on stave Silicon sensor Readout chip Bump bond connection 1.9cm×2.0cm Current ATLAS Pixel Modules

Some Other Possibilities: Vertical Integration Ideal solution for reducing material and easing assembly in detector system is to integrate electronics and sensors into a single item … if affordable This has been a “dream” for many years More complex detectors, low mass Liberate us from bump/wire bonding Many different aspects of these new technologies such as SLID (solid liquid inter-diffusion), TSV (through silicon vias), ICV (inter-chip vias) as well as more highly integrated concepts. Commercial technologies becoming available for custom design: IBM, NEC, Elpida, OKI, Tohoku, DALSA, Tezzaron, Ziptronix, Chartered, TSMC, RPI, IMEC…….. Mostly wafer-level integration and progress still quite slow

Some Issues for Discussion  Numbers of assemblies needed (often somewhere between “few of” and “industrial scale”)  Often sensor wafer already diced or wafer dimensions different from that for ASICs  Sensors and ASICs of non-standard thicknesses  Needs of prototyping and of production both need addressing  Often using pre-existing ASICs  Issues of access and availability  Large area (thin) single assemblies required, with high yield at manageable costs, to affordably populate arrays of up to several m 2