VHDL Programming Fundamentals Presented By Dr. Pradyut Kumar Biswal Department of Electronics, IIIT Bhubaneswar

What does HDL stand for? HDL is short for Hardware Description Language (VHDL – VHSIC Hardware Description Language) (Very High Speed Integrated Circuit) IIIT BhubaneswarDr. P. K. Biswal2

History of VHDL  1981 : Department of Defense, USA launches the Very High Speed Integrated Circuits (VHSIC) project.  1983 : Request for Proposal (RFP) issued by US Air Force to develop a language for hardware design description. The winner was a team composed of Intermetrics, IBM and TI.  1985 : VHDL version 7.2 made available.  1986 : Initial suite of support software released. IEEE starts effort of standardizing VHDL. IIIT Bhubaneswar3Dr. P. K. Biswal

History of VHDL  1987 : IEEE-1076 Standard released, VHDL-87.  1993 : Revised IEEE-1076 Standard released, VHDL-93.  2002 : Added IEEE synthesis and IEEE math packages, VHDL  2008 : Added generic types VHDL-2008 (Also known as VHDL 4.0). IIIT Bhubaneswar4Dr. P. K. Biswal

Compared to schematic diagrams - More standardized & portable - Easier to create - More concise - Easier to comment - Easier to read - Faster to simulate Schematics / layouts can be automatically generated from VHDL by logic synthesis IIIT BhubaneswarDr. P. K. Biswal5 Why use VHDL

IIIT BhubaneswarDr. P. K. Biswal6 VHDL Coding

IIIT BhubaneswarDr. P. K. Biswal7 VHDL features  Case insensitive  inputa, INPUTA and InputA are refer to same variable  Comments  ‘--’ until end of line  If you want to comment multiple lines, ‘--’ need to be put at the beginning of every single line  Statements are terminated by ‘;’  Signal assignment:  ‘<=’  User defined names:  letters, numbers, underscores (‘_’)  start with a letter

IIIT BhubaneswarDr. P. K. Biswal8 Reserved VHDL keywords VARIABLE WAIT WHEN WHILE WITH XNOR XOR RETURN SELECT SEVERITY SIGNAL SHARED SLA SLL SRA SRL SUBTYPE THEN TO TRANSPORT TYPE UNAFFECTED UNITS UNTIL USE OF ON OPEN OR OTHERS OUT PACKAGE PORT POSTPONED PROCEDURE PROCESS PURE RANGE RECORD REGISTER REM REPORT ROL ROR IN INERTIAL INOUT IS LABEL LIBRARY LINKAGE LITERAL LOOP MAP MOD NAND NEW NEXT NOR NOT NULL DISCONNECT DOWNTO ELSE ELSIF END ENTITY EXIT FILE FOR FUNCTION GENERATE GENERIC GROUP GUARDED IF IMPURE ABS ACCESS AFTER ALIAS ALL AND ARCHITECTURE ARRAY ASSERT ATTRIBUTE BEGIN BLOCK BODY BUFFER BUS CASE COMPONENT CONFIGURATION CONSTANT

bit values: '0', '1' boolean values: TRUE, FALSE integer values: -2,147,483,647 to 2,147,483,647 std_logic values: 'U','X','1','0','Z','W','H','L','-' ‘ U’ -- Uninitialized ‘X’ -- Forcing unknown ‘0’ -- Forcing zero ‘1’ -- Forcing one ‘Z’ -- High impedance ‘W’ -- Weak Unknown ‘L’ -- Weak Low ‘H’ -- Weak High ‘-’ -- Don’t care type std_logic is resolved std_ulogic; Std_logic_vector (n downto 0); Std_logic_vector (0 upto n); IIIT BhubaneswarDr. P. K. Biswal9 Data Types

IIIT BhubaneswarDr. P. K. Biswal10 VHDL structure  Library  Definitions, constants  Entity  Interface  Architecture  Implementation, function

Include library ieee; before entity declaration. ieee.std_logic_1164 defines a standard for designers to use in describing interconnection data types used in VHDL modeling. ieee.std_logic_arith provides a set of arithmetic, conversion, comparison functions for signed, unsigned, std_ulogic, std_logic, std_logic_vector. Ieee.std_logic_unsigned provides a set of unsigned arithmetic, conversion, and comparison functions for std_logic_vector. IIIT BhubaneswarDr. P. K. Biswal11 Standard Libraries

Every VHDL design description consists of at least one entity / architecture pair, or one entity with multiple architectures. The entity section is used to declare I/O ports of the circuit. The architecture portion describes the circuit’s behavior. Standardized design libraries are included before entity declaration. IIIT BhubaneswarDr. P. K. Biswal12 Basic Form of VHDL Code

IIIT BhubaneswarDr. P. K. Biswal13 Entity Declaration Example: Entity test is Port( A,B,C,D: in std_logic; E: out std_logic); End test; An entity declaration describes the interface of the component. PORT clause indicates input and output ports. An entity can be thought of as a symbol for a component.

PORT declaration establishes the interface of the object to the outside world. Three parts of the PORT declaration Name - Any identifier that is not a reserved word. Mode - In, Out, Inout, Buffer Data type - Any declared or predefined datatype. Sample PORT declaration syntax: IIIT BhubaneswarDr. P. K. Biswal14 Port Declaration

Architecture declarations describe the operation of the component. Define functionality of the chip Many architectures may exist for one entity, but only one may be active at a time. An architecture is similar to a schematic of the component. IIIT BhubaneswarDr. P. K. Biswal15 Architecture Declaration

IIIT BhubaneswarDr. P. K. Biswal16 Architecture X = A AND B; Y = C AND D; E = X OR Y; ARCHITECTURE BEHAVIOR OF TEST IS SIGNAL X,Y : STD_LOGIC; BEGIN X <= (not A) AND B; Y <= C AND D; E <= X OR Y; END BEHAVIOR;

 There are three modeling styles: Data flow Structural Behavioral (Sequential) IIIT BhubaneswarDr. P. K. Biswal17 Modeling Styles

IIIT BhubaneswarDr. P. K. Biswal18 VHDL Hierarchy

VHDL provides two different types of execution: sequential and concurrent. Different types of execution are useful for modeling of real hardware. Supports various levels of abstraction. Sequential statements view hardware from a “programmer” approach. Concurrent statements are order-independent and asynchronous. IIIT BhubaneswarDr. P. K. Biswal19 Sequential vs Concurrent Statements

IIIT BhubaneswarDr. P. K. Biswal20 Data flow Style

IIIT BhubaneswarDr. P. K. Biswal21 Logical operators defined in VHDL NOT AND NAND OR NOR XOR XNOR

IIIT BhubaneswarDr. P. K. Biswal22 Structural Style

IIIT BhubaneswarDr. P. K. Biswal23 Sequential Style

Circuits can be described like a netlist. Components can be customized. Large, regular circuits can be created. Structural VHDL describes the arrangement and interconnection of components. Behavioral descriptions, on the other hand, define responses to signals. Structural descriptions can show a more concrete relation between code and physical hardware. Structural descriptions show interconnects at any level of abstraction. IIIT BhubaneswarDr. P. K. Biswal24 Structural Style

The component instantiation is one of the building blocks of structural descriptions. The component instantiation process requires component declarations and component instantiation statements. Component instantiation declares the interface of the components used in the architecture. At instantiation, only the interface is visible. The internals of the component are hidden. IIIT BhubaneswarDr. P. K. Biswal25 Structural Statements

The component declaration declares the interface of the component to the architecture. IIIT BhubaneswarDr. P. K. Biswal26 Component Declaration

The instantiation statement maps the interface of the component to other objects in the architecture. IIIT BhubaneswarDr. P. K. Biswal27 Component Instantiation

IIIT BhubaneswarDr. P. K. Biswal28 Component Instantiation Syntax The instantiation has 3 key parts Name Component type Port map

 Logic operators  AND, OR, NAND, NOR, XOR, XNOR (XNOR in VHDL’93 only!!)  Relational operators  =, /=,, >=  Addition operators  +, -, &  Multiplication operators  *, /, mod, rem  Miscellaneous operators  **, abs, not IIIT BhubaneswarDr. P. K. Biswal29 Built-In Operators

Allows for sequential statements Declared within the architecture block Multiple processes executed concurrently Statements within each process executed sequentially IIIT BhubaneswarDr. P. K. Biswal30 Behavioral Description: Processes

Syntax: : process(sensitivity list) begin end process;  Sensitivity List Defines what a process is dependent on List of signals in the system Process will execute when any of these signals change  Can use constructs such as if statements in a process IIIT BhubaneswarDr. P. K. Biswal31 Processes: Syntax

 IF-THEN-ELSE Only statements in the first condition matched will be Executed Nesting allowed, each level adds more multiplexing or other additional logic, so should be done carefully  CASE-WHEN Good when all branching is based on single condition  LOOP, WHILE-LOOP, FOR-LOOP Repetition  WAIT UNTIL (boolean), WAIT FOR (time expression), WAIT ON (signal) -- waits for event on that signal IIIT BhubaneswarDr. P. K. Biswal32 Sequential Statements (Inside Process)

IIIT BhubaneswarDr. P. K. Biswal33 4 to 1 MUX using case library ieee; use ieee.std_logic_1164.all; -- 4 to 1 mux entity mymux is port (A, B, C, D : in std_logic; Sel : in std_logic_vector ( 0 to 1 ); Q : out std_logic); end mymux; architecture mux4 of mymux is begin mux_proc : process ( A, B, C, D, Sel ) begin case Sel is when "00" => Q <= A; when "01" => Q <= B; when "10" => Q <= C; when "11" => Q <= D; when others => Q <= ‘X’; end case; end process mux_proc; end mux4;

IIIT BhubaneswarDr. P. K. Biswal34 architecture mux4 of mymux is begin mux_proc : process ( A, B, C, D, Sel ) begin if (Sel = “00”) then Q <= A; elsif (Sel = “01”) then Q <= B; elsif (Sel = “10”) then Q <= C; else Q <= D; end if; end process mux_proc; end mux4; 4 to 1 MUX using IF

IIIT BhubaneswarDr. P. K. Biswal35 library ieee; use ieee.std_logic_1164.all; entity decoder_using_case is port ( enable :in std_logic; -- Enable for the decoder binary_in :in std_logic_vector (2 downto 0);-- 3-bit Input decoder_out :out std_logic_vector (7 downto 0) ); -- 8-bit Output end entity; 3 to 8 Decoder architecture behavior of decoder_using_case is begin process (enable, binary_in) begin decoder_out <= X”00"; if (enable = '1') then case (binary_in) is when “000" => decoder_out <= X”01"; when “001" => decoder_out <= X”02"; when “010" => decoder_out <= X”04"; when “011" => decoder_out <= X”08"; when “100" => decoder_out <= X”10"; when “101" => decoder_out <= X”20"; when “110" => decoder_out <= X”40"; when “111" => decoder_out <= X”80"; when others => decoder_out <= X”00"; end case; end if; end process; end architecture;

For positive edge triggered: If (clk’event and clk = ‘1’) then For negative edge triggered: If (clk’event and clk = ‘0’) then IIIT BhubaneswarDr. P. K. Biswal36 Flip-flop

SIGNAL reset, clock, d, q :std_logic; PROCESS (reset, clock) -- reset and clock are in the sensitivity list to -- indicate that they are important inputs to the process BEGIN -- IF keyword is only valid in a process IF (reset = ’0’) THEN q <= 0; ELSIF (clock’EVENT AND clock = ’1’) THEN q <= d; END IF; END PROCESS; IIIT BhubaneswarDr. P. K. Biswal37 D Flip-flop This is a D Flip-flop with asynchronous and active low reset

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY dffe IS PORT( rst, clk, d : IN std_logic; q : OUT std_logic ); END dffe; Write behavioral architecture for Active high asynchronous reset, negative edge triggered D flip-flop. IIIT BhubaneswarDr. P. K. Biswal38 D Flip-flop ARCHITECTURE synthesis1 OF dffe IS BEGIN PROCESS (rst, clk) BEGIN IF (rst = ‘1’) THEN q <= ‘0’; ELSIF (clk’EVENT) AND (clk = ‘0’) THEN q <= d; END IF; END PROCESS; END synthesis1;

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY dffe IS PORT( rst, clk, d : IN std_logic; q : OUT std_logic ); END dffe; Write behavioral architecture for Active low synchronous reset, negative edge triggered D flip-flop. IIIT BhubaneswarDr. P. K. Biswal39 D Flip-flop ARCHITECTURE synthesis1 OF dffe IS BEGIN PROCESS (rst, clk) BEGIN IF (clk’EVENT) AND (clk = ‘0’) THEN IF (rst = ‘0’) THEN q <= ‘0’; ELSE q <= d; END IF; END PROCESS; END synthesis1;