1 Packet Network Simulator-on-Chip Henry Wong Danyao Wang University of Toronto Connections 2009 ECE Graduate Symposium

2 Networks are ubiquitous… Network protocols are getting more complex e.g. Peer-to-peer swarms Networks are getting more complex Bigger, faster, and essential Need a way to simulate large networks quickly and accurately Image source:

3 Existing Methods Software simulation Cheap, fast, accurate ← choose one! e.g. ns2, OPNET Emulation Interface with real traffic -> non-deterministic Experimentation Most accurate, can be expensive e.g. PlanetLab

4 Our Proposal Network simulator on FPGA Advantages Fast: Less overhead and more parallelism than software Challenges 1. FPGA compile can take hours 2. Hardware is more difficult to customize 3. Simulation size limited by the capacity of FPGA

5 Simulator on FPGA 1. Generic on-chip interconnect to connect end node, router, and packet queue models Simulate different networks without recompiling the FPGA 2. Use soft processors instead of hard nodes More configurability 3. Hierarchical synchronization Fine-grain within a chip, coarse-grain across chips Scalable to larger networks

6 How does this work? User Network PQ0 PQ1 On-chip architecture TG PQ RT

7 On-Chip Interconnect

8 Current Status Cycle-accurate C++ simulation model Estimated 100x speedup over ns2 (at 50MHz) 58% throughput vs. ideal crossbar 0.41 simulation timesteps / cycle Hardware development in progress ComponentLEsMem (bits)Fmax Router2041Kb> 200MHz PacketQueue3002Kb106 MHz TrafficGen9414Kb90 MHz InterconnectEst. ~3K--Est. ~60 MHz