Presentation is loading. Please wait.

Presentation is loading. Please wait.

To be smart or not to be? Siva Subramanian Polaris R&D Lab, RTP Tal Lavian OPENET Lab, Santa Clara.

Similar presentations


Presentation on theme: "To be smart or not to be? Siva Subramanian Polaris R&D Lab, RTP Tal Lavian OPENET Lab, Santa Clara."— Presentation transcript:

1 To be smart or not to be? Siva Subramanian Polaris R&D Lab, RTP Tal Lavian OPENET Lab, Santa Clara

2 State of the network Plenty of bandwidth –Optical core Increasing demand for services –Gateways –Network Service nodes –Content Switches –Network Caches Evolving network

3 Evolution of the network Virus Scanning Bridging Routing QoS Network Monitoring Firewall VPN Intrusion Detection Load Balancing Instructions per Packet Complexity CoreEdge C C CoreEdge

4 Current Mode of Operation Application specific solutions Hardware/Software design and deployment cycles takes years Ad-hoc solutions create complex networks Multiple network management solutions

5 Answer – Part I Flexibility Programmability (open interfaces)

6 Processing Requirements Bridging Routing QoS Network Monitoring Firewall VPN Intrusion Detection Virus Scanning Load Balancing 1002000+ Instructions per Packet Complexity

7 Need for Power Computational Complexity 32-bit Processor @ 500 MIPS How much can you do with it? Need for high performance computing technology deeper in the network 100BaseT OC48 Time/Word # Insts 320ns160 13ns 7

8 Answer – Part II High Performance Computing Technologies –Configurable Computing –Parallel Processing

9 Configurable Computing Configurable Computing: Programmable logic ( FPGA ) coupled to Processor (  P ) Customized for each application Application PP ASIC PP Tasks FPGA PP CC

10 How does CC work? Customised hardware operations Concurrent operations float D, I, K, R; int A = 100;... while ( A != 0 ) { temp = I * K; D = R + temp; A - - ; } I K + * R D FPGA

11 The power of CC DCT implementation –Xilinx FPGA 180 times faster than 32- bit processor @ 266MHz Vector computations –50MHz FPGA roughly 10 times faster than 300MHz Pentium CPU

12 Evolution of routers – Phase I Centralized CPU-based Router Control + Forwarding functions combined CPU Routing Software Slow Forwarding Processor based Router based Router Control separated from Forwarding CPU Control Plane Forwarding Processor Wire-Speed Forwarding Processor

13 Forward Plane Control Plane Traffic Packets Towards Open Networking Switching Fabric CPU System Forwarding Processor Forwarding Rules Forwarding Processor Forwarding Rules Forwarding Processor Forwarding Rules... Java Runtime Support Java-based Network Services Forward API

14 Node Architecture Control Plane Forward Plane Compute Plane Forward API Compute API Network Services Compute Services

15 Evolution of Routers – Phase II Control, Compute and Forward planes Forward-only flows are not seen by Compute plane Control plane can modify behavior of Compute and Forward planes Forward Control CPU ASIC Compute NPUCCCPU

16 Open Networking Abstract Compute & Forward Plane interfaces Technology reuse over a range of NORTEL platforms Control Plane Forward Plane Compute Plane Forward API Compute API Network Services Compute Services

17 Work in progress… NORTEL R&D activities –POLARIS lab –OPENET lab Research Target –“Smart” node architectures –Open architectures –High Performance Computing technologies

18 Summary Future network node architecture –Open networking –Programmable networking –High performance computing Benefits to NORTEL –Rapid service deployment –Third-party value-added services –Increased market penetration

19 To learn more … http://www.openetlab.org/ http://www.ieee-pin.org/ http://comet.columbia.edu/openarch http://comet.columbia.edu/opensig http://www.cpixforum.org/


Download ppt "To be smart or not to be? Siva Subramanian Polaris R&D Lab, RTP Tal Lavian OPENET Lab, Santa Clara."

Similar presentations


Ads by Google