PS VFE & PS/SPD FE Electronics Status and Plans 16 January 2008 LPC Clermont.

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Presentation transcript:

PS VFE & PS/SPD FE Electronics Status and Plans 16 January 2008 LPC Clermont

2 PS/SPD FEB Status, Installation & Inventory  Production & Tests Finished: 112 PS/SPD FEB produced (including 2 prototypes) 100 boards installed in Pit 8 & Functional 10 spare LPC & Functional  2A patch 2 problematic boards LPC ( PCB or connector issues )  Installation Finished: PRS0 to PRS6, FE boards are individually Functional PRS7: No 380 V PSU / ‘burnt’ by inverted pair in power cable connector / connector now repaired C Side: CROC V4 with ‘last’ firmware in all PRS crates A Side: No CROCs

3 VFE Powering & Cooling  Water cooling is in the pipes since beginning December  No leakage reported since then  All VFE on C side powered simultaneously / ‘All’ Functional  Temperature is Monitored:  varies from 16 ºC (All OFF) to less than 25 º C (All ON) Allowed automatisation of test process Move to calibration tasks

4 So We Moved Upstairs …

5 VFE & FE RJ45 Pendant Issue ‘Automated’ Test on PSDAQHVC01W of RJ45 VFE to FE connection: measure pedestal noise ‘we keep an eye on this’ RJ45 connection FE / VFE is sensitive: Cable seems well plugged mechanically but impedance miss-match on one of the 4 pairs  Loss of signal amplitude: up factor ~10  Reflections: seen with LED flashes for ~0.2 % of channels During cabling: False both FE/VFE side: ~2% cables Post cabling: False connection rate ~0.2% / month only on FE side But, constant human activity on the ECAL platform …

6 VFE Sagita Pendant Issue  Sagita on back of VFE boards  lost of connection for CLOCK signal / Due to: - Stresses through VFE RJ45 cables / in detector movements ?  Statistics: - C side: 7 / 50 VFE lost from may to July 2 / 50 VFE lost from July to September 2 / 50 VFE lost from September to November No loss during December / 1 VFE (SM2T-01 still KO) - A side: 2 / 50 VFE lost from may to September No loss from September to December VFE electronics VFE connectors RJ45 CLOCK Signal power Schematics of VFE ( 2 boards + connectors): sagitta caused by ?

7 DAQ: FEB / CROC Synchronisation From FEB signal to CROC: 2 phaser values to tune for synchronisation Valid phases diagram for PRS3 (Over all PRS FEB slots) KO OK Issue in PRS3 for FEB /CROC synchronisation Related to DAQ of slots ~4-7 & 8-11  CROC FE-PGA 2&3 PRS0-2 OK (but data left on PSDAQHVC01W …)

8 DAQ: FE / VFE Synchronisation 1) Sample VFE integration 2) Re-sample in FEB FE-PGA plateau From VFE signal to FEB FE-PGA: 3 phaser values to tune for synchronisation Validity diagrams against ADC phase based on FE & VFE pedestal signals For all FEB/VFE C side  ADC multiple of 8 are pathologic

9 Trigger: PRS Neighbours TOP/BOTTOM PRS Trigger bits TOP/BOTTOM neighbours: Transmitted via RJ45 Errors data reception for some slots/boards  Systematic FEB slot #2: No data received !!? ( ) FEBs I/Os validated in Clermont Backplane issues ? Not seen in Clermont Try to re-plug FEBs in faulty slots Tests Trigger ECAL/PRS, PRS/TVB & PRS LEFT/RIGHT (backplane) ongoing some re-cabling on PRS/TVB

10 Outlook Commissioning / Calibration work ongoing …  DAQ: Phase validity diagrams w/ new CROC Firmware  Issue in PRS3 FEB/CROC phases  Trigger: Link tests ongoing  Issue with some PRS TOP/BOTTOM slots: no data received  Pendant:  VFE CLOCK loss / RJ45 stress  Monitor FE RJ45 connections (~automated)