ELE22MIC Lectures 6 and 7 Assembly Language Instruction Set Overview, Part 3 –Addressing Modes –Add, Push, Pull, Jump –Conditional Jumps

LDS#STACK;initialize start of stack 68HC11 Register Set

M68HC Addressing Modes Immediate Direct Extended Indexed Inherent Relative

Immediate Addressing Mode The data for the operation immediately follows the instruction The # symbol must be used to select immediate addressing Examples: LDAA #$42 ; Load Acc.A with the value $42 -> Machine Codes: LDX #DEEE ; Load Index Register X with hex value DEEE -> Machine Codes CE DE EE

Direct Addressing Modes Direct Addressing can access an operand located in the first 256 bytes of memory, $0000..$00FF An 8-bit memory address specifies where: data is read from, or data is written to. Examples: –LDAA $42; AccA = Memory[$42] -> Machine Code –STAA$FF; Memory[FF] = AccA –LDX $12; IX = Memory[$12]..[$13]

Extended Addressing Modes Extended Addressing uses 16-bit address to specify A 16-bit memory address specifies where: data is read from, or data is written to. Examples: –LDAA $4231; AccA = Memory[$4321] -> Machine Code B –STAA$2000; Memory[$2000] = AccA –LDX $1234; IX = Memory[$1234]..[$1235]

Indexed Addressing Modes (1) Indexed addressing always uses one of two index registers X or Y. Instruction Format: –Operation Offset, Index_Register –Offset is an unsigned 8-bit value (0..255) added to the contents of the index register –The value of the index register is not altered. –Addition is modulo 65536

Indexed Addressing Modes (2) –EXAMPLE: LDAA 42, X ; AccA = Memory[42+X] -> Machine Code A6 42

Inherent Addressing Modes All data for the instruction is within the CPU. ABA; A = A + B -> Machine code $1B MUL; D = A * B -> Machine code $3D NEGA ; A = -A -> Machine code $40 ABX; X = X + A -> Machine code $3A INX; X = X + 1 -> Machine code $08 SEC; CarryFlag= 1 -> Machine code$0D TAB; B = A -> Machine code $16

Addressing Modes Review Immediate, Direct, Extended, Indexed, Inherent, Relative LDAA > B LDAA 42 -> LDAA #42 -> LDAA 42, X -> A6 42 BRA > 20 1E (at $2000) ABA-> 1B No memory to memory moves w/o register

Major Instruction Set Categories ARITHMETIC BRANCH, JUMP & SUBROUTINE CALL/RETURN COMPARE DATA MOVEMENT LOGICAL

ARITHMETIC Instructions ADDITION, SUBTRACTION, TWOS COMPLEMENT (NEGATION), DECREMENT & INCREMENT MULTIPLY & DIVIDE ARITHMETIC/LOGICAL SHIFT/ROTATE BINARY CODED DECIMAL CLEAR (bit(s) = 0) & SET (bit(s) = 1) COMPARE & TEST CONDITION CODE MANIPULATION CONDITIONAL Branches SIGNED / UN-SIGNED NUMERIC INTERPRETATION DATA MOVEMENT Push/Pull Load/Store Register Transfer Registers Exchange Registers INTERRUPT HANDLING: LOGICAL LOGICAL AND LOGICAL EXCLUSIVE OR LOGICAL OR ONES-COMPLEMENT (NOT) MISCELLANEOUS

ADDITION ABAA = A + B ABXIX = IX + B ABYIY = IY + B ADCAA = A + M + CarryFlag ADCBB = B + M + CarryFlag ADDAA = A + M ADDBB = B + M ADDDD = D + M

SUBTRACTION SBAA = A - B SBCAA = A - M - CarryFla SBCBB = B - M - CarryFlag SUBAA = A - M SUBBB = B - M SUBDD = D - M

NEGATION NEGM = -M NEGAA = -A BEGBB = -B TWOS COMPLEMENT

DECREMENT DECM = M - 1 DECAA = A - 1 DECBB = B - 1 DESSP = SP - 1 DEXIX = IX - 1

INCREMENT INCM = M + 1 INCAA = A + 1 INCBB = B + 1 INSSP = SP + 1 INXIX = IX + 1 INYIY = IY + 1

MULTIPLY / DIVIDE MULTIPLY –MULD = A * B DIVIDE –IDIVIX = D / IX, D = D % IX (Unsigned Integer Divide) –FDIVIX = D / IX, D = D % IX (Unsigned fractional divide - Radix point assumed left of bit 15 of both operands)

Arithmetic/Logical Shift & Rotate

ARITHMETIC SHIFT LEFT: (Multiply by 2) ASLArithmetic Shift Left (M) ASLAArithmetic Shift Left (A) ASLBArithmetic Shift Left (B) ASLDArithmetic Shift Left (D) RIGHT: (Divide By 2, Sign-Extend MSBit) ASRArithmetic Shift Right (M) ASRAArithmetic Shift Right (A) ASRBArithmetic Shift Right (B)

LOGICAL SHIFT LEFT: (Same as ASL) LSLLogical Shift Left (M) LSLALogical Shift Left (A) LSLBLogical Shift Left (B) LSLDLogical Shift Left (D) RIGHT: (Zero Fill MSBit) LSRLogical Shift Right (M) LSRALogical Shift Right (A) LSRBLogical Shift Right (B) LSRDLogical Shift Right (D) ROTATE LEFT: (extended multiply) ROLROtate Left (M) ROLAROtate Left (A) ROLBROtate Left (B) RIGHT: (extended divide) RORROtate Right (M) RORAROtate Right (A) RORBROtate Right (B) BINARY CODED DECIMAL (BCD) DAADecimal Adjust after Addition Branch & Jump BRABranch Always BRNBranch Never JMPJump to Address JSRJump to Subroutine NOPNo OPeration ; i.e do nothing but fetch next instruction CLEAR (bit(s) = 0) & SET (bit(s) = 1) CLRM = 0 CLRAA = 0 CLRBB = 0 BCLRClear Bits (M) BSETSet Bits (M) COMPARE & TEST CONDITION CODE MANIPULATION CLCCarryFlag = 0Clear Carry Flag CLVOVerflowFlag = 0Clear Overflow Flag SECCarryFlag = 1Set Carry Flag SEVOVerflowFlag = 1Set Overflow Flag TAPCCR = A Transfer A to Condition Codes Register (CCR) TPAA = CCR Transfer CCR to A CONDITIONAL Branches BEQBranch if EQual BNEBranch if Not Equal BCCBranch if CarryFlag is Clear BCSBranch if CarryFlag is Set BRCLRBranch if bits clear BRSETBranch if bits set Branches for SIGNED NUMERIC INTERPRETATION BMI; Branch if MInus BPL; Branch if PLus BVS;Branch if oVerflow Set BVC;Branch if oVerflow Clear BLT;Branch if Less Than BGE;Branch if Greater-Than or Equal-to BLE;Branch if Less-Than or Equal-to Branches for UN-SIGNED NUMERIC INTERPRETATION BHI; Branch if HIgher than BHS;Branch if Higher or Same BLS;Branch if Lower or Same BLO;Branch if Lower DATA MOVEMENT Push - Push register value onto stack PSHAM[SP--] = A The contents of the A register is pushed onto the stack - i.e. stored into memory at the address contained in the stack pointer; then the stack pointer is decremented. –PSHBM[SP--] = B PSHXM[SP--] = IX.LOW ; M[SP--] = IX.HIGH PSHYM[SP--] = IY.LOW ; M[SP--] = IY.HIGH Pull - Pull (POP) value from stack to Register PULA; A = M[++Sp] The stack pointer is first incremented, and then Accumulator A is popped off the stack - i.e. loaded from memory where the stack pointer is pointing. PULB; B = M[++SP] PULX; X.HIGH = M[++SP] ; X.LOW = M[++SP] PULY; Y.HIGH = M[++SP] ; Y.LOW = M[++SP] Load Register LDAAA = M LDABB = M LDDD = M LDSSP = M LDXX = M LDYY = M Store Register Transfer Registers TAB; A = B TBA; B = A TSX; IX = SP + 1 TSY; IY = SP + 1 TXS; SP = IX - 1 TXY; SP = IY - 1 Exchange Registers XGDX;D IX XGDY;D IY INTERRUPT HANDLING: CLI; Clear interrupt Mask SEI; Set interrupt Mask SWI; Software Interrupt RTI; Return from Interrupt WAI; Wait for interrupt LOGICAL LOGICAL AND –ANDA; A = A & M –ANDB;B = B & M LOGICAL EXCLUSIVE OR –EORA;A = A ^ M –EORB;B = B ^ M LOGICAL OR –ORAA; A = A | M –ORAB; B = B | M ONES COMPLEMENT (NOT) –COM; M = M# –COMA; A = A# –COMB; B = B# MISCELLANEOUS STOP; Stop clocks TEST; Special test mode (different meaning to 80x86)

ROTATE LEFT: (extended multiply) ROLROtate Left (M) ROLAROtate Left (A) ROLBROtate Left (B) RIGHT: (extended divide) RORROtate Right (M) RORAROtate Right (A) RORBROtate Right (B)

CLEAR/BIT CLEAR/BIT SET CLEAR (bit(s) = 0) & SET (bit(s) = 1) CLRM = 0 CLRAA = 0 CLRBB = 0 BCLRClear Bits (M) BSETSet Bits (M)

Jumps JUMP address (0..FFFF) JMPJump to Address JSRJump to Subroutine RTSReTurn from Subroutine NOPNo OPeration ; i.e do nothing but fetch next instruction

Branch & Jump BRANCH ( ) & JUMP (0..FFFF) Branch BRABranch Always BRNBranch Never BSR Branch to SubRoutine

COMPARE & TEST CONDITION CODE MANIPULATION CLCCarryFlag = 0CLear Carry Flag CLVOVerflowFlag = 0 SECCarryFlag = 1SEt Carry Flag SEVOVerflowFlag = 1 TAPCCR = ATransfer A to CCR TPAA = CCRTransfer CCR to A CCR = Condition Codes Register

CONDITIONAL BRANCHES (1) CONDITIONAL Branches BEQBranch if EQual BNEBranch if Not Equal BCCBranch if Carry Flag is Clear BCSBranch if Carry Flag is Set BRCLRBRanch if bits CLeaR BRSETBRanch if bits SET

CONDITIONAL BRANCHES (2) SIGNED COMPARISON BMIBranch if Minus BPLBranch if PLus BVSBranch if oVerflow Set BVCBranch if oVerflow Clear BGTBranch if Greater-Than > BGEBranch if Greater-than or Equal-to >= BLEBranch if Less-than or Equal-to <= BLTBranch if Less Than <

CONDITIONAL BRANCHES (3) UN-SIGNED COMPARISON BHIBranch if HIgher than > BHSBranch if Higher or Same>= BLSBranch if Lower or Same<= BLOBranch if Lower<

PUSH Push - Push register value onto stack PSHAM[SP--] = A The contents of the A register is pushed onto the stack - i.e. stored into memory at the address contained in the stack pointer; then the stack pointer is decremented. PSHB M[SP--] = B PSHX M[SP--] = IX.LOW ; M[SP--] = IX.HIG PSHY M[SP--] = IY.LOW ; M[SP--] = IY.HIGH Pull - Pull (POP) value from stack to Register PULA; A = M[++Sp] The stack pointer is first incremented, and then Accumulator A is popped off the stack - i.e. loaded from memory where the stack pointer is pointing. PULB; B = M[++SP] PULX; X.HIGH = M[++SP] ; X.LOW = M[++SP] PULY; Y.HIGH = M[++SP] ; Y.LOW = M[++SP] Load Register LDAAA = M LDABB = M LDDD = M LDSSP = M LDXX = M LDYY = M Store Register Transfer Registers TAB; A = B TBA; B = A TSX; IX = SP + 1 TSY; IY = SP + 1 TXS; SP = IX - 1 TXY; SP = IY - 1 Exchange Registers XGDX;D IX XGDY;D IY INTERRUPT HANDLING: CLI; Clear interrupt Mask SEI; Set interrupt Mask SWI; Software Interrupt RTI; Return from Interrupt WAI; Wait for interrupt LOGICAL LOGICAL AND –ANDA; A = A & M –ANDB;B = B & M LOGICAL EXCLUSIVE OR –EORA;A = A ^ M –EORB;B = B ^ M LOGICAL OR –ORAA; A = A | M –ORAB; B = B | M ONES COMPLEMENT (NOT) –COM; M = M# –COMA; A = A# –COMB; B = B# MISCELLANEOUS STOP; Stop clocks TEST; Special test mode (different meaning to 80x86)

PULL Pull - Pull (POP) value from stack to Register PULA; A = M[++Sp] The stack pointer is first incremented, and then Accumulator A is popped off the stack - i.e. loaded from memory where the stack pointer is pointing. PULB ; B = M[++SP] PULX ; X.HIGH = M[++SP] ; X.LOW = M[++SP] PULY ; Y.HIGH = M[++SP] ; Y.LOW = M[++SP] Load Register LDAAA = M LDABB = M LDDD = M LDSSP = M LDXX = M LDYY = M Store Register Transfer Registers TAB; A = B TBA; B = A TSX; IX = SP + 1 TSY; IY = SP + 1 TXS; SP = IX - 1 TXY; SP = IY - 1 Exchange Registers XGDX;D IX XGDY;D IY INTERRUPT HANDLING: CLI; Clear interrupt Mask SEI; Set interrupt Mask SWI; Software Interrupt RTI; Return from Interrupt WAI; Wait for interrupt LOGICAL LOGICAL AND –ANDA; A = A & M –ANDB;B = B & M LOGICAL EXCLUSIVE OR –EORA;A = A ^ M –EORB;B = B ^ M LOGICAL OR –ORAA; A = A | M –ORAB; B = B | M ONES COMPLEMENT (NOT) –COM; M = M# –COMA; A = A# –COMB; B = B# MISCELLANEOUS STOP; Stop clocks TEST; Special test mode (different meaning to 80x86)

Load Register LDAAA = M LDABB = M LDDD = M LDSSP = M LDXX = M LDYY = M

Store Register STAAM = A STABM = B STSM = SP STDM = D STXM = IX STYM = IY

Transfer Registers TAB; A = B TBA; B = A TSX; IX = SP + 1 TSY; IY = SP + 1 TXS; SP = IX - 1 TXY; SP = IY - 1

Exchange Registers XGDX;D IX XGDY;D IY

INTERRUPT HANDLING: CLI; Clear interrupt Mask SEI; Set interrupt Mask SWI; Software Interrupt RTI; Return from Interrupt WAI; Wait for interrupt

LOGICAL (1) LOGICAL AND –ANDA; A = A & M –ANDB; B = B & M LOGICAL EXCLUSIVE OR –EORA; A = A ^ M –EORB; B = B ^ M

LOGICAL (2) LOGICAL OR –ORAA; A = A | M –ORAB; B = B | M ONES COMPLEMENT (NOT) –COM; M = M# –COMA; A = A# –COMB; B = B#

MISCELLANEOUS STOP; Stop clocks TEST; Special test mode (different meaning to 80x86 instruction) BINARY CODED DECIMAL (BCD) DAADecimal Adjust after Addition

AS11 Constant Definition ' ASCII character $ hexadecimal octal constant % binary constant digit decimal constant

AS11 Assembler Directives EQU - EQUATE –Used to define constants for example: –OUTSTR EQU $E3D9 ORG xxxx - ORIGINATE –Locate the program at the specified address, xxxx

AS11 Assembler Expressions Expressions may consist of symbols, constants or the character“*” (denoting the current value of the program counter) joined together by one of the operators: + - * / % & | ^.

AS11 Assembler Expressions The operators are same as C: +add -subtract *multiply /divide %modulo &bitwise AND |bitwise OR ^bitwise EXCLUSIVE-OR

Examples Shift Left & Right Binary Multiplication Binary Division Extending for larger numbers

AS11 Assembler Invocation To invoke the cross-assembler AS11 in a dos box enter: AS11 file1 (file2...) -option1 -option2 Options: l enable output listing. nol disable output listing (default). cre generate cross reference table. s generate a symbol table. c enable cycle count info. noc disable cycle count info.

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