C HAPTER F IVE S YNCHRONOUS S EQUENTIAL L OGIC 1

2 S EQUENTIAL C IRCUITS Combinational Circuit Memory Elements Inputs Outputs Asynchronous Synchronous Combinational Circuit Flip-flops Inputs Outputs Clock

3 L ATCHES SR Latch (cross coupled NOR) S R Q 0 QQ’ Q = Q 0 Initial Value

4 L ATCHES SR Latch S R Q 0 Q Q’ Q = Q 0

5 L ATCHES SR Latch S R Q 0 Q Q’ Q = 0 Q = Q 0

6 L ATCHES SR Latch S R Q 0 Q Q’ Q = 0 Q = Q 0 Q = 0

7 L ATCHES SR Latch S R Q 0 Q Q’ Q = 0 Q = Q 0 Q = 1

8 L ATCHES SR Latch S R Q 0 Q Q’ Q = 0 Q = Q 0 Q = 1

9 L ATCHES SR Latch S R Q 0 Q Q’ Q = 0 Q = Q 0 Q = 1 Q = Q’ 0

10 L ATCHES SR Latch S R Q 0 Q Q’ Q = 0 Q = Q 0 Q = 1 Q = Q’ 0

11 L ATCHES SR Latch S RQ 0 Q0Q Q=Q’=0 No change Reset Set Invalid S R Q 0 Q=Q’= Q0Q0 Invalid Set Reset No change

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13 C ONTROLLED L ATCHES SR Latch with Control Input (operates with signal level) C S RQ 0 x x Q0Q Q0Q Q=Q’Q=Q’ No change Reset Set Invalid

14 C ONTROLLED L ATCHES D Latch (Transparent Latch) C D (data)Q 0 x Q0Q No change Reset Set C Timing Diagram D Q t Output may change

15 C ONTROLLED L ATCHES D Latch ( D = Data ) C DQ 0 x Q0Q No change Reset Set C Timing Diagram D Q Output may change

16 F LIP -F LOPS Controlled latches are level-triggered Flip-Flops are edge-triggered It operates with signal transitions C CLKPositive Edge CLKNegative Edge

17 F LIP -F LOPS Master-Slave D Flip-Flop D Latch (Master) DCDC Q D Latch (Slave) DCDC QQD CLK D Q Master Q Slave Looks like it is negative edge-triggered MasterSlave

18 F LIP -F LOPS Edge-Triggered D Flip-Flop DQ Q DQ Q Positive Edge Negative Edge S R

19 F LIP -F LOP C HARACTERISTIC E QUATIONS Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) No change Reset Set Toggle

20 F LIP -F LOP C HARACTERISTIC E QUATIONS Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) No change Reset Set Toggle

21 F LIP -F LOP C HARACTERISTIC E QUATIONS Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) No change Reset Set Toggle

22 F LIP -F LOP C HARACTERISTIC E QUATIONS Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) No change Reset Set Toggle

23 F LIP -F LOP C HARACTERISTIC E QUATIONS Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) K 0100 J1101 Q Q(t+1) = JQ’ + K’Q

24 F LIP -F LOPS JK Flip-Flop JQ QK D = JQ’ + K’Q

25 F LIP -F LOPS T Flip-Flop D = TQ’ + T’Q = T  Q JQ QK T DQ Q T D = JQ’ + K’Q TQ Q

26 F LIP -F LOP C HARACTERISTIC T ABLES DQ Q DQ(t+1) Reset Set JKQ(t+1) 00Q(t)Q(t) Q’(t) No change Reset Set Toggle JQ QK TQ Q TQ(t+1) 0Q(t)Q(t) 1Q’(t) No change Toggle

27 F LIP -F LOPS WITH D IRECT I NPUTS Asynchronous Reset DQ Q R Reset RDCLKQ(t+1) 0xx0

28 F LIP -F LOPS WITH D IRECT I NPUTS Asynchronous Reset DQ Q R Reset RDCLKQ(t+1) 0xx0 10 ↑ 0 11 ↑ 1

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30 A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS The State State = Values of all Flip-Flops Example A B = 0 0

31 A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS Flip-Flop input equations D A = A(t) x(t)+B(t) x(t) = A x + B x D B = A’(t) x(t) = A’ x State equations A(t+1) = D A B(t+1) = D B Output equation y(t) = [A(t)+ B(t)] x’(t) = (A + B) x’

32 A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS State Table (Transition Table) A(t+1) = A x + B x B(t+1) = A’ x y(t) = (A + B) x’ Present State Input Next State Output ABxABy t+1 t t

33 A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS State Table (Transition Table) A(t+1) = A x + B x B(t+1) = A’ x y(t) = (A + B) x’ Present State Next StateOutput x = 0x = 1x = 0x = 1 ABABAB yy t+1 t t

34 A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS State Diagram /00/0 0/10/1 1/01/0 1/01/0 1/01/0 1/01/00/10/1 0/10/1 AB input/output Present State Next StateOutput x = 0x = 1x = 0x = 1 ABABAB yy

35 A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS D Flip-Flops Example : DQ Q x CLK y A Present State Input Next State A xy A ,11 01,10 A(t+1) = D A = A  x  y

36 A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS JK Flip-Flops Example : J A = BK A = B x’ J B = x’K B = A  x A(t+1) = J A Q’ A + K’ A Q A = A’B + AB’ + Ax B(t+1) = J B Q’ B + K’ B Q B = B’x’ + ABx + A’Bx’ Present State I/P Next State Flip-Flop Inputs ABxABJAJA KAKA JBJB KBKB

37 A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS JK Flip-Flops Example : Present State I/P Next State Flip-Flop Inputs ABxABJAJA KAKA JBJB KBKB

38 A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS T Flip-Flops Example : T A = B xT B = x y = A B A(t+1) = T A Q’ A + T’ A Q A = AB’ + Ax’ + A’Bx B(t+1) = T B Q’ B + T’ B Q B = x  B Present State I/P Next State F.F Inputs O/P ABxABTATA TBTB y

39 A NALYSIS OF C LOCKED S EQUENTIAL C IRCUITS T Flip-Flops Example : Present State I/P Next State F.F Inputs O/P ABxABTATA TBTB y /00/0 1/01/0 0/00/0 1/01/0 1/01/0 1/11/1 0/00/0 0/10/1

T HE P ROBLEMS : 5.3, 5.4, , 5.9, 5.10,

41 S TATE R EDUCTION AND A SSIGNMENT State Reduction Reductions on the number of flip-flops and the number of gates. A reduction in the number of states result in a reduction in the number of flip-flops. The external inputs and outputs requirements do not change. Start with state diagram shown in Fig Fig. 5.25State diagram

42 S TATE R EDUCTION Only the input-output sequences are important. Two circuits are equivalent Have identical outputs for all input sequences; The number of states is not important. Fig. 5.25State diagram State:aabcdeffgfga Input: Output:

43 Equivalent states Two states are said to be equivalent For each member of the set of inputs, they give exactly the same output and send the circuit to the same state or to an equivalent state. One of them can be removed.

44 Reducing the state table e = g (remove g ); d = f (remove f );

45 The reduced finite state problem State:aabcdeddedea Input: Output:

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47 S TATE A SSIGNMENT To design a sequential circuit, it is necessary to assign unique coded binary values to the states. Three possible binary state assignments. ( m states need n - bits, where 2 n >= m ). Unused states are treated as don’t-care conditions during the design.

48 Any binary number assignment is satisfactory as long as each state is assigned a unique number.

49 D ESIGN P ROCEDURE Design Procedure for sequential circuit The word description of the circuit behavior to get a state diagram; State reduction if necessary; Assign binary values to the states; Obtain the binary-coded state table; Choose the type of flip-flops; Derive the simplified flip-flop input equations and output equations; Draw the logic diagram;

D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS Example : (Sequence Detector) Detect 3 or more consecutive 1’s in a string of bits coming through an input line S 0 / 0S 1 / 0 S 3 / 1S 2 / StateA B S0S0 0 S1S1 0 1 S2S2 1 0 S3S3 1

D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS Example : Detect 3 or more consecutive 1’s Present State Input Next State Output ABxABy S0S0 S1S1 S3S3 S2S2 0 / 0 1 / 0 0 / 1 0 / 0 1 / 1 0 / 0 1 / 0

D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS Example : Detect 3 or more consecutive 1’s Present State Input Next State Output ABxABy A(t+1) = D A (A, B, x) = ∑ (3, 5, 7) B(t+1) = D B (A, B, x) = ∑ (1, 5, 7) y (A, B, x) = ∑ (6, 7) D Synthesis using D Flip-Flops

D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS WITH D F.F. Example : Detect 3 or more consecutive 1’s D A (A, B, x) = ∑ (3, 5, 7) = A x + B x D B (A, B, x) = ∑ (1, 5, 7) = A x + B’ x y (A, B, x) = ∑ (6, 7) = A B D Synthesis using D Flip-Flops B 0010 A0110 x B 0100 A0110 x B 0000 A0011 x

D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS WITH D F.F. Example : Detect 3 or more consecutive 1’s D A = A x + B x D B = A x + B’ x y = A B D Synthesis using D Flip-Flops

F LIP -F LOP E XCITATION T ABLES Present State Next State F.F. Input Q(t)Q(t)Q(t+1)D Present State Next State F.F. Input Q(t)Q(t)Q(t+1)JK (No change) 0 1 (Reset) 0 x 1 x x 1 x (Set) 1 1 (Toggle) 0 1 (Reset) 1 1 (Toggle) 0 0 (No change) 1 0 (Set) Q(t)Q(t)Q(t+1)T

D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS WITH JK F.F. Example : Detect 3 or more consecutive 1’s Present State Input Next State Flip-Flop Inputs ABxAB JAJA KAKA JBJB KBKB x 1 x x 1 x 0 x 1 x 0 J A (A, B, x) = ∑ (3) K A (A, B, x) = ∑ (4, 6) J B (A, B, x) = ∑ (1, 5) K B (A, B, x) = ∑ (2, 3, 6) JK Synthesis using JK F.F. 0 x 1 x x 1 0 x 1 x x 1 x 0

D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS WITH JK F.F. Example : Detect 3 or more consecutive 1’s J A = B xK A = x’ J B = xK B = A’ + x’ JK Synthesis using JK Flip-Flops B 0010 Axxxx x B xxxx A1001 x B 01xx A01xx x B xx11 Axx01 x

D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS WITH T F.F. Example : Detect 3 or more consecutive 1’s Present State Input Next State F.F. Input ABxABT A T B T Synthesis using T Flip-Flops T A (A, B, x) = ∑ (3, 4, 6) T B (A, B, x) = ∑ (1, 2, 3, 5, 6)

D ESIGN OF C LOCKED S EQUENTIAL C IRCUITS WITH T F.F. Example : Detect 3 or more consecutive 1’s T A = A x’ + A’ B x T B = A’ B + B  x T Synthesis using T Flip-Flops B 0010 A1001 x B 0111 A0101 x

The problems are: 5.12, 5.13, 5.14, 5.15, 5.16, 5.18, 60