February 22-25, 2010 Designers Work Less with Quality Formal Equivalence Checking by Orly Cohen, Moran Gordon, Michael Lifshits, Alexander Nadel, and Vadim.

Slides:



Advertisements
Similar presentations
Exploiting SAT solvers in unbounded model checking
Advertisements

Copyright 2000 Cadence Design Systems. Permission is granted to reproduce without modification. Introduction An overview of formal methods for hardware.
Copyright © 2009,Intel Corporation. All rights reserved. Auto ECO Flow Development For Functional ECO Using Efficient Error Rectification Method Based.
Introducing Formal Methods, Module 1, Version 1.1, Oct., Formal Specification and Analytical Verification L 5.
Proofs from SAT Solvers Yeting Ge ACSys NYU Nov
Annoucements  Next labs 9 and 10 are paired for everyone. So don’t miss the lab.  There is a review session for the quiz on Monday, November 4, at 8:00.
Aaron Bradley University of Colorado, Boulder
Theoretical Program Checking Greg Bronevetsky. Background The field of Program Checking is about 13 years old. Pioneered by Manuel Blum, Hal Wasserman,
Boosting Minimal Unsatisfiable Core Extraction. Agenda Introduction and motivation New algorithms ◦ Generic scheme ◦ Resolution-based algorithm ◦ Selector-variable-based.
Department of Electrical and Computer Engineering M.A. Basith, T. Ahmad, A. Rossi *, M. Ciesielski ECE Dept. Univ. Massachusetts, Amherst * Univ. Bretagne.
ECE Synthesis & Verification1 ECE 667 Spring 2011 Synthesis and Verification of Digital Systems Verification Introduction.
SAT Algorithms in EDA Applications Mukul R. Prasad Dept. of Electrical Engineering & Computer Sciences University of California-Berkeley EE219B Seminar.
Automated Extraction of Inductive Invariants to Aid Model Checking Mike Case DES/CHESS Seminar EECS Department, UC Berkeley April 10, 2007.
Formal verification Marco A. Peña Universitat Politècnica de Catalunya.
1 Linear-time Reductions of Resolution Proofs Omer Bar-Ilan Oded Fuhrmann Shlomo Hoory Ohad Shacham Ofer Strichman Technion.
272: Software Engineering Fall 2012 Instructor: Tevfik Bultan Lecture 4: SMT-based Bounded Model Checking of Concurrent Software.
USING SAT-BASED CRAIG INTERPOLATION TO ENLARGE CLOCK GATING FUNCTIONS Ting-Hao Lin, Chung-Yang (Ric) Huang Graduate Institute of Electrical Engineering,
Streamline Verification Process with Formal Property Verification to Meet Highly Compressed Design Cycle Prosenjit Chatterjee, nVIDIA Corporation.
7/13/2003BMC A SAT-Based Approach to Abstraction Refinement in Model Checking Bing Li, Chao Wang and Fabio Somenzi University of Colorado at Boulder.
Digitaalsüsteemide verifitseerimise kursus1 Digitaalsüsteemide verifitseerimine IAF0620, 5.0 AP, E Jaan Raik IT-208,
Enhancing and Integrating Model Checking Engines Robert Brayton Alan Mishchenko UC Berkeley June 15, 2009.
1 Automatic Refinement and Vacuity Detection for Symbolic Trajectory Evaluation Orna Grumberg Technion Haifa, Israel Joint work with Rachel Tzoref.
Using Formal Verification to Exhaustively Verify SoC Assemblies by Mark Handover Kenny Ranerup Applications Engineer ASIC Consultant Mentor Graphics Corp.
Inferring Specifications to Detect Errors in Code Mana Taghdiri Presented by: Robert Seater MIT Computer Science & AI Lab.
TECH Computer Science NP-Complete Problems Problems  Abstract Problems  Decision Problem, Optimal value, Optimal solution  Encodings  //Data Structure.
Semi-automatic Property Generation for the Formal Verification of a Satellite On-board System Wesley Gonçalves Silva.
1 Hybrid-Formal Coverage Convergence Dan Benua Synopsys Verification Group January 18, 2010.
Incremental formal verification of hardware Hana Chockler Alexander Ivrii Arie Matsliah Shiri Moran Ziv Nevo IBM Research - Haifa.
ABC: A System for Sequential Synthesis and Verification BVSRC Berkeley Verification and Synthesis Research Center Robert Brayton, Niklas Een, Alan Mishchenko,
Simultaneously Learning and Filtering Juan F. Mancilla-Caceres CS498EA - Fall 2011 Some slides from Connecting Learning and Logic, Eyal Amir 2006.
An Overview of Hardware Design Methodology Ian Mitchelle De Vera.
Learning Symbolic Interfaces of Software Components Zvonimir Rakamarić.
Cut-Based Inductive Invariant Computation Michael Case 1,2 Alan Mishchenko 1 Robert Brayton 1 Robert Brayton 1 1 UC Berkeley 2 IBM Systems and Technology.
1 IAF0620, 5.0 AP, Exam Jaan Raik ICT-524, , Digital systems verification.
Properties Incompleteness Evaluation by Functional Verification IEEE TRANSACTIONS ON COMPUTERS, VOL. 56, NO. 4, APRIL
Saleem Sabbagh & Najeeb Darawshy Supervisors: Mony Orbach, Technion & Ilia Averbouch, IBM Started at: Spring 2012 Duration: Semester.
Preprocessing in Incremental SAT Alexander Nadel 1, Vadim Ryvchin 1,2, and Ofer Strichman 2 1 – Intel, Haifa, Israel 2 – Technion, Haifa, Israel SAT’12,
SAT-Based Model Checking Without Unrolling Aaron R. Bradley.
Manufacture Testing of Digital Circuits
C OMPUTING U NSAT C ORES O F B OOLEAN A ND SMT F ORMULAS Computing Small Unsatisfiable Cores in Satisfiability Modulo Theories Alessandro Cimatti, Alberto.
Introduction to Hardware Verification ECE 598 SV Prof. Shobha Vasudevan.
Error Explanation with Distance Metrics Authors: Alex Groce, Sagar Chaki, Daniel Kroening, and Ofer Strichman International Journal on Software Tools for.
1 Alan Mishchenko Research Update June-September 2008.
On the Relation Between Simulation-based and SAT-based Diagnosis CMPE 58Q Giray Kömürcü Boğaziçi University.
Variable-Time-Frame Gate-Level Abstraction Alan Mishchenko Niklas Een Robert Brayton Alan Mishchenko Niklas Een Robert Brayton UC Berkeley UC Berkeley.
Bit-Vector Optimization ALEXANDER NADER AND VADIM RYVCHIN INTEL TACAS 2016.
Efficient Generation of Small Interpolants in CNF (for Model Checking)
ASIC Design Methodology
Types for Programs and Proofs
Synthesis for Verification
Solving Linear Arithmetic with SAT-based MC
Deriving small unsatisfiable cores with dominators
Enhancing PDR/IC3 with Localization Abstraction
New Directions in the Development of ABC
Alon Flaisher Alon Gluska Eli Singerman Intel Corporation
Mining backbone literals in incremental SAT
Optimal Redundancy Removal without Fixedpoint Computation
Property Directed Reachability with Word-Level Abstraction
Canonical Computation without Canonical Data Structure
Canonical Computation Without Canonical Data Structure
Scalable and Scalably-Verifiable Sequential Synthesis
Improvements to Combinational Equivalence Checking
GLA: Gate-Level Abstraction Revisited
Resolution Proofs for Combinational Equivalence
Efficient MUS Extraction with Resolution
Recording Synthesis History for Sequential Verification
Canonical Computation without Canonical Data Structure
Improved Design Debugging using Maximum Satisfiability
SAT-based Methods: Logic Synthesis and Technology Mapping
Faster Extraction of High-Level Minimal Unsatisfiable Cores
Presentation transcript:

February 22-25, 2010 Designers Work Less with Quality Formal Equivalence Checking by Orly Cohen, Moran Gordon, Michael Lifshits, Alexander Nadel, and Vadim Ryvchin Intel

Agenda Formal Equivalence Checking (FEC) in Parts Using Assume- Guarantee FEC Flow Description and the Importance of Assumptions Minimizing Assumptions –Naive Approaches –FEC as SAT Problem –Minimizing Assumptions Using SAT Comparison of SAT-Based and Naive Minimization Approaches Impact of Assumption Minimization on the Manual Debug Effort Conclusions and Recommendations Michael Lifshits, Intel 2 of 14

Assume-Guarantee in Formal Equivalence Checking (FEC) FEC proves the equivalence of 2 designs (e.g. schematics vs. RTL) FEC is done on small sub-blocks (slices) suitable for formal tools’ capacity Slices’ inputs are restricted with assumptions, e.g. in SVA DUT with Properties Inputs Outputs Assumption Assertion Michael Lifshits, Intel 3 of 14

Origins of Assumptions Manually added assumptions Design intent properties –ABV methodology Schematic Assumptions –appear in the standard cells library –save transistors, area, power Michael Lifshits, Intel INVERSE(a,b) 4 of 14

FEC Stages – the Importance of Assumptions Assumptions must be proved relative to the driving logic smaller set of assumptions is better! “Intel CPU project arrived with a dead A0 silicon due to a missed assumption verification step” Michael Lifshits, Intel Assumptions must be proved relative to the driving logic 5 of 14

Minimizing the Assumptions Set Naive approaches: Static Structural Analysis Iterative Trial and Error alg. Michael Lifshits, Intel MinAssump := ∅ // start without assumptions while verification fails and MinAssump  All_Assump do Try proving with assumptions in MinAssump if pass  Done Use the counterexample (CEX) and find A ∈ All_Assump : A ∈ MinAssump and A contradicts with CEX Add (at most K) such assumptions to MinAssump // K=20 return MinAssump 6 of 14

Formal as SAT Problem Most FEC tools are implemented with SAT-based FV engines FEC is reduced to a propositional formula: F=a AND b OR c… SAT solver proofs the lack of counterexamples for F; –CEX is an assignment for {a,b,c..} | F==TRUE O 1 O 2 O 1 O 2 ’same( O 1, O 2 )(t), F=XOR( O 1, O 2 ’ )(t), fails when F=TRUE NOTS 1 (t)AND(S 1 (t)… S 1 =T, S 2 =T, ENB=T NOTS 1 (t)AND(S 1 (t)… checked for t=1,2.. fails when S 1 =T, S 2 =T, ENB=T Unsatisfiable coreUnsatisfiable core – sub-formulas required for the proof ENB S1S1S1S1 S2S2S2S2 O 1 =NOTS 1 O 2 ’=(S 1 ANDS 2 ANDENB) OR (O 2 AND^ENB) Michael Lifshits, Intel 7 of 14

UNSAT CORE SAT Formula assumptions Minimizing Assumptions Using SAT The projection of UNSAT CORE onto the assumptions is the subset of assumptions required for the proof Minimization at the SAT level  minimal number of assumptions Simple approach: Our approach: Michael Lifshits, Intel 8 of 14

Iterative SAT Algorithm to Minimize Assumptions Solve formula F: SAT(F) with All_Assump Extract UNSAT CORE: UC MinAssump := A ∈ Assump: A ∩ Proj(UC) ≠ ∅ // start with all used for all A ∈ MinAssump do // try removing 1 assumption, reuse learning in SAT SAT(F) with MinAssump / {A}// solve F without A If pass  MinAssump := MinAssump /{A}, update UC return MinAssump Michael Lifshits, Intel 9 of 14 SAT-Based Minimization vs. Naive Trial and Error 50% assumptions in most cases, and dramatically fewer in some

UNSAT CORE Projection vs. Iterative Minimization (ours) It is justified mainly when minimizing the core is more important than reducing the run-time SAT-Based Minimization Algorithms Comparison Michael Lifshits, Intel 10 of 14 Run time (hours) Remaining properties

Impact of Assumption Reduction on the Manual Debug Effort All properties (including assumptions) are formally verified SQL database used to store the verification results Combined verification statusCombined verification status – status of the recursive set of used assumptions: For each used-by-FEC (UBF) property P Get the set of assumptions (Assump) used to verify a property P For each A i ∈ Assump Assump i := set of assumptions used to verify A i Assump all = Assump ∪ Assump i … ∪ Assump n // a recursive set if all A i ∈ Assump all pass status(P) = pass else status(P) = conditional Michael Lifshits, Intel 11 of 14

Impact of Assumption Reduction on the Manual Debug Effort 36% more properties passed Number of properties in FEC is large – a large amount of manual effort is saved to the design team Michael Lifshits, Intel 12 of 14 % of all properties

Reducing the number of used assumptions decreases manual debug time and computational effort UNSAT core-based techniques are much more effective than naive techniquesTradeoff between the reduction effectiveness and the run-timeDifferent SAT-based assumption minimization techniques fit various FEC stages Assumptions minimization is more important for RTL and SCH equivalence verification than for the RTL assumption verification RTL assumptions verification complexity is greater than RTL and SCH equivalence Iterative SAT-based assumption minimization for RTL and SCH equivalence Assumption reduction (UNSAT core projection) for RTL assumption verification Conclusion and Recommendations Michael Lifshits, Intel 13 of 14

Backup Michael Lifshits, Intel 14 of 14

SAT-Based Minimization vs. Naive Trial and Error 22 random microprocessor design blocks % indicate the improvement compared to the iterative Time (logarithmic scale) Michael Lifshits, Intel “naive” trial and error SAT-based Half as many assumptions in most cases, and dramatically fewer in some 50% == ½ assumptions 15 of 14