June 9, s Massachusetts Institute of Technology 6.11s: Design of Motors, Generators and Drive Systems Switching Patterns and Simple Implementation J. L. Kirtley Jr. June 9, 2005 ©2005, J.L. Kirtley Jr.

June 9, s Here is your basic three phase bridge

June 9, s Suppose we have this situation:

June 9, s Here is one way of switching that circuit: The arrows designate when a switch is ON

June 9, s Here is what is on in State 0: V a = V, V b = V, V c = 0 V n = 2V/3

June 9, s V a = 0, V b = V, V c = 0 V n = V/3 Here is what is on in State 1:

June 9, s V a = 0, V b = V, V c = V V n = 2V/3 Here is what is on in State 2:

June 9, s V a = 0, V b = 0, V c = V V n = V/3 Here is what is on in State 3:

June 9, s V a = V, V b = 0, V c = V V n = 2V/3 Here is what is on in State 4:

June 9, s V a = V, V b = 0, V c = 0 V n = V/3 Here is what is on in State 5:

June 9, s Voltages: Line-Line Voltages are well defined

June 9, s To generate switching signals: Totem Pole A is High in states 0, 4 and 5 Totem Pole B is High in states 0, 1 and 2 Totem Pole C is High in states 2, 3 and 4 This allows us to use very simple logic: A = S0 + S4 + S5 B = S0 + S1 + S2 C = S2 + S3 + S4

June 9, s To generate switch signals Note that either top or bottom switch is on in each phase Generation of states: we will do this a bit later (see below)

June 9, s This ‘six pulse’ switching strategy: Makes good use of the switching devices Also requires ‘shoot-through’ delays Has very simple logic We propose an alternative switching strategy Makes minimally less effective use of switches Uses a little more logic But does not risk shoot through

June 9, s Here is a comparison of switching strategies 180 degree six- pulse 120 degree six pulse Give up a little timing between switch closings

June 9, s Switches Q_1 and Q_5 are on: State0 Va = V, Vb = 0, Vc = V/2

June 9, s Switches Q_1 and Q_6 are on: State1 Va = V, Vc = 0, Vb = V/2

June 9, s Switches Q_2 and Q_6 are on: State2 Vb = V, Vc = 0, Va = V/2

June 9, s Switches Q_2 and Q_4 are on: State3 Va = 0, Vb = V, Vc = V/2

June 9, s Switches Q_3 and Q_4 are on: State4 Va = 0, Vc = V, Vb = V/2

June 9, s Switches Q_3 and Q_5 are on: State5 Vc = V, Vb = 0, Va = V/2

June 9, s This switching pattern results in these voltages

June 9, s Switches turn on: Q1State_0 OR State_1 Q2State_2 OR State_3 Q3State_4 OR State_5 Q4State_3 OR State_4 Q5State_1 OR State_5 Q6State_1 OR State_2 Each switch is on for two states

June 9, s So here is how to do it 3 bit input to ‘138 selects one of 8 outputs Active low output! ‘138 has 3 enable inputs: two low, one high

June 9, s NAND (Not AND) Is the same as Negative Input OR The ‘138 output is ‘active low’: Matching bubbles makes an OR function

June 9, s Now we must generate six states in sequence If we have a ‘clock’ with rising edges at the right time interval we can use a very simple finite state machine This could be a counter, reset when it sees ‘5’

June 9, s Here is a good counter to use: 74LS163 This is a loadable counter: don’t need that feature Clear function is synchronous: so it clears only ON a clock edge Part is ‘edge triggered’: changes state on a positive clock edge P and T are enables: must pull them high

June 9, s We already detect state 5 with the ‘138

June 9, s Here is how to wire those two parts Count Seq: …

June 9, s Just for reference: some useful pinouts Note ‘00 has the same pinout as all two input gates

June 9, s Variable Voltage: do the Pulse Width Modulation thing

June 9, s Why do we need to PWM only the top switches? What happens with you turn OFF switch Q1?