SLAAC SLD Update Steve Crago USC/ISI September 14, 1999 DARPA

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 2 Second-Level Detection Detection Indexer (SLD) Focus of Attention ESAR Image LPMMSECRM Identification Belief Management (Fusion Executive) MPM Joint STARS Advance Workstation (JAWS) ATR Results Display PGA Second-Level Detection SAR Image T72 Annotated SAR Image T72 *Not Joint STARS imagery Goal 200x performance improvement over old custom hardware

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 3 Interface l Input n Chips (regions of interest, 8-bit pixels) n Bright and Surround Templates (expected SAR reflection and absorption, 1-bit pixels) l Output n Hypothetical target matches

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 4 Chip *Not Joint STARS imagery 64 pixels 48 pixels Template Search Space 32 pixels 15 pixels Chip SLD Search Space

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 5 Computation SM(i, j) =  B(u,v)M(i+u, j+v), 8-bit additions TH(i,j) = SM(i,j)/BC - Bias BS(i, j) =  B(u,v)[M(i+u, j+v)<TH(i,j)] 8-bit comparisons 1-bit additions SS(i, j) =  S(u,v)[M(i+u, j+v)<TH(i,j)] 8-bit comparisons 1-bit additions P1 Shape Sum P2 Threshold P3 Bright Sum P4 Surround Sum Q(i, j) = [BS(i, j) + SS(i, j)]* P5 Hit Quality Calculate average intensity of chip pixels at positions expected to reflect signal For each position in the search space: Count number of pixels that exceed average intensity under “on” bright template pixels Counter number of pixels that are less than average intensity under “on” surround template pixels Check hit conditions, calculate hit quality, and return 2 highest hit quality scores

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 6 ACS Implementation l Compute independent search space pixels in parallel ( computational elements per FPGA) Template Memory Packed 8-bit pixels Packed bits Host Highest Quality Hits (Chip, Template IDs, location) Chip Pixels Adaptive Computing Element

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 7 I/O Requirements l Each eight-bit chip pixel used for 550 operations per match task l Each FIFO element contains 8 chip pixels l Each FIFO elements contains enough operands for 3600 operations  I/O will not be a bottleneck any time soon!

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 8 Memory Requirements l Template pixels are only 1 bit (each memory access provides 18 operands) l Computation uses one template bit per cycle l Pixels are broadcast to all compute elements that are working on a single match task l Multiple ports for parallel match tasks reduce logic complexity  Memory bandwidth will not be a bottleneck any time soon, but ports are helpful!

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 9 Virtex Features l Chip pixel alignment pipeline n BlockSelectRAM+ can replace logic cells n Could buy some speed l Template-specific reconfiguration n Potential speedup due to sparseness of templates n Clear win not yet clear

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 10 Performance Projections

Steve Crago USC INFORMATION SCIENCES INSTITUTE Page 11 Schedule l Single-chip implementation working l Full Wildforce implementation: 9/99 l SLAAC-2 implementation: 9/99? l Virtex implementation: ??? n Remap to use additional logic should be easy n Utilization of BlockSelectRAM+ will take a little more time, but straightforward