1 CS/COE0447 Computer Organization & Assembly Language Chapter 2 Part 2

2 Continuing from Chapter 2 Part 1 Starts with modified versions of Part 1’s last 5 slides

3 But first: errors on green card p1. lbu I 0/24hex  lbu I 24hex lhu I 0/25hex  lbu I 25hex lw I 0/23hex  lw I 23hex EG: machine code for lbu $8,2($7) sll and srl: replace “rs” with “rt” (example later)

4 ANDI and ORI lui I R[rt] = {immediate,16’b0} andi I R[rt] & ZeroExtImm (3) (3) ZeroExtImm = {16{1’b0},immediate} In Verilog: 16'h704f // a 16-bit hex number 1’b0 // a 1-bit binary number lui $t1, 0x7F40 addi $t2, $t1, 0x777 andi $t3, $t2, 0x5555 Above and ori version in lecture

5 Long Immediates (e.g., memory addresses!) Sometimes we need a long immediate, e.g., 32 bits MIPS requires that we use two instructions –lui $t0, 0xaa55 –ori $t0, $t0, 0xcc33 –Note: this wouldn’t work if ori used SignExtImm rather than ZeroExtImm! (“or” with 0 == copy; like adding 0 in arithmetic) $t $t0

6 Loading a memory address.data places values in memory starting at 0x bits are needed to specify memory addresses. 1 instruction is impossible: the address would take up the entire instruction!! (no room for the opcode!!) la $t0, 0x is a pseudo instruction – not implemented in the hardware lui $1, 4097 la $t0, 0x ori $8, $1, 8 lw $t1, 0($t0) # look at green card to # understand this addr mode

7 A program Get sample1.asm from the schedule Load it into the simulator Figure out the memory contents, labels Trace through the code

8.data # sample1.asm a:.word 3,4 c:.word 5,6.text la $t0,c # address of c la $t1,k # address of k lw $s0,0($t0) # load c[0] lw $s1,4($t1) # load k[1] slt $s3,$s0,$s1 # if c[0] < k[1], $s3 = 1, else $s3 = 0 beq $s3,$0,notless # if c[0] < k[1] swap their values sw $s0,4($t1) sw $s1,0($t0) notless:.data k:.word 0xf,0x11,0x12

9 Quick Exercise From A-57: load immediate li rdest, imm e.g., li $t0,0xffffffff “Move the immediate imm into register rdest” [nothing is said about sign or 0 extension] What type of instruction is this? E.g., is this an R-format instruction? Perhaps an I-format one? … Please explain.

10 Quick Exercise Answer In class

11 Memory Transfer Instructions To load/store a word from/to memory: –LOAD: move data from memory to register lw $t3, 4($t2)# $t3  M[$t2 + 4] –STORE: move data from register to memory sw $t4, 16($t1)# M[$t1 + 16]  $t4 Support for other data types than 32-bit word is needed –16-bit half-word “short” type in C 16-bit processing is common in signal processing lhu and sh in MIPS –8-bit byte “char” type in C 8-bit processing is common in controller applications lbu and sb

12 Machine Code Example swap: sll$t0, $a1, 2 add$t1, $a0, $t0 lw$t3, 0($t1) lw$t4, 4($t1) sw$t4, 0($t1) sw$t3, 4($t1) jr$ra void swap(int v[], int k) { int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; } $a0: pointer to array $a1: k

13 Memory View Viewed as a large, single-dimensional 8-bit array with an address (“byte address”) A memory address is an index into the array BYTE …

14 Addresses Specify Byte Locations –Address of first byte –Addresses are aligned: addresses are multiples of X, where X is the number of bytes. –word (4 bytes) addresses are multiples of 4; half-word (2 bytes) addresses are multiples of A 000B 32-bit Words BytesAddr. 000C 000D 000E 000F Half Words Addr = ?? Addr = ?? Addr = ?? Addr = ?? C A 000C 000E In Class: match up with format of memory shown by simulator

15 Example of Memory Allocation.data b2:.byte 2,3,4.align 2.word 5,6,7.text la $t0,b2 lbu $t2,0($t0) # $t2 = 0x02 lbu $t2,1($t0) # $t2 = 0x03 lbu $t2,3($t0) # $t2 = 0x00 (nothing was stored there) lbu $t2,4($t0) # $t2 = 0x00 (top byte of the 5 word) lbu $t2,7($t0) # $t2 = 0x05 (bottom byte of the 5 word)

16 Byte Ordering How should bytes within multi-byte words be ordered in memory? Conventions –“Big Endian” machines (including MIPS machines) Least significant byte has highest address.data.word 3 (0x ; 03 is the least sig. byte) 03 is in –“Little Endian” machines Least significant byte has lowest address 03 would be in

17 Byte Ordering Example Big Endian –Least significant byte has highest address Little Endian –Least significant byte has lowest address Example –Suppose variable x has 4-byte representation 0x –Suppose address of x is 0x100 0x1000x1010x1020x x1000x1010x1020x Big Endian Little Endian

18 Memory Organization 2 32 bytes with byte addresses from 0 to 2 32 – words with byte addresses 0, 4, 8, …, 2 32 – half-words with byte addresses 0, 4, 8, …, 2 32 – 2 –Suppose addresses were 5 bits. Bytes: 0…31; Words: 0,4,8,12,14,16,20,24,28, i.e., 0,4,..,2^5 – 4; Half-words: 0,2,4,…, 28, 30, i.e., 0,2,…,2^5-2. WORD … Unsigned numbers in n bits: 0 to 2^n - 1 Eg: 3 bits: 0 to 7 4 bits: 0 to 15 5 bits: 0 to 31

19 Misalignment Example Misaligned accesses (errors!) –lw $t1, 3($zero) –lbu $t1, 1($zero) Alignment issue does not exist for byte accesses …

20 Shift Instructions Bit-wise logic operations Examples –sll $t0, $s0, 4# $t0 = $s0 << 4 –srl $s0, $t0, 2# $s0 = $t0 >> 2 These are the only shift instructions in the core instruction set Green card is wrong for sll and srl; “rs” should be “rt” NameFieldsComments R-formatop NOT USED rtrdshamtfunctshamt is “shift amount”

21 Shift Instructions Variations in the MIPS-32 instruction set: –Shift amount can be in a register (“shamt” field not used) sllv, srlv, srav –Shift right arithmetic (SRA) keeps the sign of a number sra $s0, $t0, 4 Pseudo instructions: –Rotate right/left: ror, rol

22.text li $t0,0x77 li $t1,-8 li $t2,3 sll $t3,$t0,3 sllv $t3,$t0,$t2 srl $t3,$t0,2 srl $t3,$t1,2 sra $t3,$t1,2 li $s0,0x li $s1,1 ror $s0,$s0,$s1

23 Control Decision-making instructions –Alter the control flow, i.e., change the “next” instruction to be executed MIPS conditional branch instructions –bne $t0, $t1, LABEL –beq $t0, $t1, LABEL Example bne $s0, $s1, LABEL add $s3, $s0, $s1 LABEL: … if (i == h) h =i+j; (i == h)? h=i+j; LABEL: YESNO

24 Control, cont’d MIPS unconditional branch instruction (jump) –j LABEL Example –f, g, and h are in registers $s3, $s4, and $s5 bne $s4, $s5, ELSE add $s3, $s4, $s5 j EXIT ELSE: sub $s3, $s4, $s5 EXIT: … if (i == h) f=g+h; else f=g–h; (i == h)? f=g+h; YESNO f=g–h EXIT

25 # while (save[i] == k) # i += 1.data save:.word 5,5,5,5,7,6,6,7.text li $s3,1 # $s3 is 1; suppose i is 1 la $s6,save # $s6 is base address of array li $s5,5 # $s5 is k; suppose k is 5 loop: sll $t1,$s3,2 add $t1,$t1,$s6 #$t1 points to save[i] lw $t0,0($t1) #$t0 = save[i] bne $t0,$s5,exitloop addi $s3,$s3,1 # i += 1 j loop exitloop: add $s6,$s3,$zero

26 # sum = 0 # for (i = 0; i < n; i++) #sum += i addi $s0,$zero,0 # $s0 sum = 0 addi $s1,$zero,5 # $s1 n = 5; arbitrary value addi $t0,$zero,0 # $t0 i = 0 loop: slt $t1,$t0,$s1 # i < n? beq $t1,$zero,exitloop # if not, exit add $s0,$s0,$t0 # sum += i addi $t0,$t0,1 # i++ j loop exitloop: add $v0,$zero,$s0 # $v0 has the sum

27 # sum = 0 # for (i = 0; i < n; i++) #sum += i addi $s0,$zero,0 # $s0 sum = 0 addi $s1,$zero,5 # $s1 n = 5; a random value addi $t0,$zero,0 # $t0 i = 0 loop: bge $t0,$s1,exitloop # i < n? PSEUDO OP! add $s0,$s0,$t0 # sum += i addi $t0,$t0,1 # i++ j loop exitloop: add $v0,$zero,$s0 # $v0 has the sum

28 Instruction Format Address in the instruction is not a 32-bit number – it’s only 16-bit –The 16-bit immediate value is in signed, 2’s complement form Addressing in branch instructions –The 16-bit number in the instruction specifies the number of “instructions” to skip –Memory address is obtained by adding this number to the PC –Next address = PC sign_extend(16-bit immediate << 2) Example –beq $s1, $s2, 100 Branch/ Immediate oprsrt16-bit immediate

29 bne $t0,$s5,exitloop addi $s3,$s3,1 j loop exitloop: add $s6,$s3,$zero 0x x x c 0x

30 Instruction Format, cont’d The address of next instruction is obtained by concatenating with PC –Next address = {PC[31:28],IMM[25:0],00} –Address boundaries of 256MB Example –j Jumpop26-bit immediate 22500

31 MIPS Addressing Modes Immediate addressing (I-format) Register addressing (R-/I-format) Base addressing (load/store) [register + offset] PC-relative addressing (beq/bne) [PC offset] Pseudo-direct addressing (j) [concatenation w/ PC] oprsrt funct immediate 26-bit address oprsrtimmediate oprsrtrdshamt oprsrtoffset oprsrtoffset op

32 Summary